中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

83 records (took 0.022 seconds)

    Load reduced memory module
    41.
    发明授权
    Load reduced memory module 有权

    公开(公告)号：US10149383B2

    公开(公告)日：2018-12-04

    申请号：US15814180

    申请日：2017-11-15

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Suresh Rajan

    IPC: G11C5/06 ,  H05K1/11 ,  G11C11/4093 ,  H05K1/18 ,  G06F15/78 ,  G11C11/408 ,  G06F13/16 ,  G06F13/40 ,  G06F1/18 ,  G11C5/04 ,  G11C7/10

    Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

    DRAM retention monitoring method for dynamic error correction
    42.
    发明授权
    DRAM retention monitoring method for dynamic error correction 有权
    用于动态纠错的DRAM保留监控方法

    公开(公告)号：US09411678B1

    公开(公告)日：2016-08-09

    申请号：US13828828

    申请日：2013-03-14

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Suresh Rajan ,  Ely Tsern ,  Thomas Vogelsang ,  Wayne Ellis

    IPC: H03M13/00 ,  G06F11/10

    CPC classification number: G06F11/1008

    Abstract: A method of operation in a memory device, comprising storing data in a first group of storage locations in the memory device, storing error information associated with the stored data in a second group of storage locations in the memory device, and selectively evaluating the error information based on a state of an error enable bit, the state based on whether a most recent access to the first group of storage locations involved a partial access.

    Abstract translation: 一种在存储器件中的操作方法，包括将数据存储在存储器件中的第一组存储位置中，将与存储的数据相关联的错误信息存储在存储器件中的第二组存储位置中，并且选择性地评估误差信息 基于错误使能位的状态，基于对第一组存储位置的最近访问是否涉及部分访问的状态。

    DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION
    44.
    发明申请
    DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION 有权
    用于动态误差校正的DRAM保持测试方法

    公开(公告)号：US20140289574A1

    公开(公告)日：2014-09-25

    申请号：US14353401

    申请日：2012-10-19

    Applicant: RAMBUS INC.

    Inventor： Ely Tsern ,  Frederick A. Ware ,  Suresh Rajan ,  Thomas Vogelsang

    IPC: G11C29/24

    CPC classification number: G06F11/1008 ,  G11C5/04 ,  G11C29/24 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4061

    Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

    Abstract translation: 公开了一种在集成电路（IC）存储器件中的操作方法。 该方法包括以第一刷新率刷新IC存储设备中的第一组存储行。 测试每行的保留时间。 对被测试给定行的测试包括以比第一刷新率慢的第二刷新率刷新。 测试可以基于存储在给定行中的数据的访问请求而中断。

    HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE
    46.
    发明公开
    HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE 审中-公开

    公开(公告)号：US20240193108A1

    公开(公告)日：2024-06-13

    申请号：US18545189

    申请日：2023-12-19

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

    IPC: G06F13/16 ,  G06F13/00 ,  G06F13/42

    CPC classification number: G06F13/1673 ,  G06F13/00 ,  G06F13/4243

    Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

    HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE
    50.
    发明申请
    HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE 有权

    公开(公告)号：US20220222189A1

    公开(公告)日：2022-07-14

    申请号：US17649773

    申请日：2022-02-02

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

    IPC: G06F13/16 ,  G06F13/00 ,  G06F13/42

    Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

Patent Agency Ranking