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公开(公告)号：US10085352B2
公开(公告)日：2018-09-25
申请号：US14872910
申请日：2015-10-01
Applicant: RF Micro Devices, Inc.
Inventor： Julio C. Costa , George Maxim , Dirk Robert Walter Leipold , Baker Scott
IPC: H01L21/50 , H01L21/56 , H01L23/48 , H05K3/30 , H05K3/28 , H01F27/24 , H01L23/31 , H01L23/36 , H01L23/373 , H01L23/498 , H05K3/46 , H05K1/18
CPC classification number: H05K3/284 , H01F17/0013 , H01F27/24 , H01F2017/0086 , H01L23/3121 , H01L23/3135 , H01L23/36 , H01L23/3737 , H01L23/49822 , H01L23/645 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0655 , H01L2224/131 , H01L2224/13147 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81815 , H01L2224/92125 , H01L2224/97 , H01L2924/15313 , H01L2924/18161 , H01L2924/19042 , H01L2924/19105 , H01L2924/3511 , H05K1/183 , H05K3/4697 , H05K2201/086 , H05K2201/1003 , H01L2924/014 , H01L2924/00014 , H01L2224/81 , H01L2224/83
Abstract: This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.
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公开(公告)号：US09992876B2
公开(公告)日：2018-06-05
申请号：US14872910
申请日：2015-10-01
Applicant: RF Micro Devices, Inc.
Inventor： Julio C. Costa , George Maxim , Dirk Robert Walter Leipold , Baker Scott
IPC: H01L21/50 , H01L21/56 , H01L23/48 , H05K3/30 , H05K3/28 , H01F27/24 , H01L23/31 , H01L23/36 , H01L23/373 , H01L23/498 , H05K3/46 , H05K1/18
Abstract: This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.
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公开(公告)号：US20170365394A9
公开(公告)日：2017-12-21
申请号：US14929608
申请日：2015-11-02
Applicant: RF Micro Devices, Inc.
Inventor： Dirk Robert Walter Leipold , George Maxim , Marcus Granger-Jones , Baker Scott
CPC classification number: H01F27/2804 , H01F2027/2809 , H01L21/0276 , H01L28/10 , H01P7/06 , H01P7/065 , H01P7/08 , H03H7/38 , H03H7/463 , H03H9/24 , H04B1/40 , H04J1/08
Abstract: Embodiments of an apparatus are disclosed that includes a first three dimensional (3D) inductor and a second 3D inductor. The first three dimensional (3D) inductor has a first conductive path shaped as a first two dimensional (2D) lobe laid over a first 3D volume. In addition, the second 3D inductor has a second conductive path, wherein the second 3D inductor is inserted into the first 3D inductor so that the second conductive path at least partially extends through the first 3D volume. Since second 3D inductor is inserted into the first 3D inductor, the 3D inductors may be coupled to one another. Depending on orientation and distances of structures provided by the 3D inductors, the 3D inductors may be weakly or moderately coupled.
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公开(公告)号：US09680440B2
公开(公告)日：2017-06-13
申请号：US14554943
申请日：2014-11-26
Applicant: RF Micro Devices, Inc.
Inventor： George Maxim , Dirk Robert Walter Leipold , Baker Scott
Abstract: Radio frequency (RF) filter structures and related methods and RF front-end circuitry are disclosed. In one embodiment, an RF filter structure includes a first terminal and a first tunable RF filter path defined between the first terminal and a second terminal. The first tunable RF filter path is tunable to provide impedance matching between the first terminal and the second terminal at a first frequency. The first frequency may be provided within a first frequency band. Additionally, the RF filter structure includes a second tunable RF filter path defined between the first terminal and the second terminal. The second tunable RF filter path is tunable to provide impedance matching between the first terminal and the second terminal at a second frequency. The second frequency may be within a second frequency band. In this manner, the RF filter structure is configured to provide impedance tuning for multiple impedance bands simultaneously.
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公开(公告)号：US09628045B2
公开(公告)日：2017-04-18
申请号：US14449913
申请日：2014-08-01
Applicant: RF Micro Devices, Inc.
Inventor： Dirk Robert Walter Leipold , George Maxim , Baker Scott , Nadim Khlat , Jayanti Jaganatha Rao
CPC classification number: H03H7/465 , H03F1/565 , H03F3/193 , H03F3/245 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/267 , H03F2200/391 , H03F2200/451 , H03F2203/7209 , H03H7/0115 , H03H7/09 , H03H7/1775 , H03H2210/012 , H03H2210/025 , H03H2210/04
Abstract: RF communications circuitry, which includes a first tunable RF filter and a second tunable RF filter, is disclosed. The first tunable RF filter is coupled to the second tunable RF filter. The RF communications circuitry operates in one of a first operating mode and a second operating mode. During the first operating mode, the second tunable RF filter receives and filters an upstream RF signal to provide a filtered RF signal. Further, during the first operating mode, the first tunable RF filter augments a frequency response of the second tunable RF filter.
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Patent Agency Ranking
公开(公告)号：US09628042B2
公开(公告)日：2017-04-18
申请号：US14554943
申请日：2014-11-26
Applicant: RF Micro Devices, Inc.
Inventor： George Maxim , Dirk Robert Walter Leipold , Baker Scott
Abstract: Radio frequency (RF) filter structures and related methods and RF front-end circuitry are disclosed. In one embodiment, an RF filter structure includes a first terminal and a first tunable RF filter path defined between the first terminal and a second terminal. The first tunable RF filter path is tunable to provide impedance matching between the first terminal and the second terminal at a first frequency. The first frequency may be provided within a first frequency band. Additionally, the RF filter structure includes a second tunable RF filter path defined between the first terminal and the second terminal. The second tunable RF filter path is tunable to provide impedance matching between the first terminal and the second terminal at a second frequency. The second frequency may be within a second frequency band. In this manner, the RF filter structure is configured to provide impedance tuning for multiple impedance bands simultaneously.
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公开(公告)号：US20160126929A1
公开(公告)日：2016-05-05
申请号：US14931165
申请日：2015-11-03
Applicant: RF Micro Devices, Inc.
Inventor： Dirk Robert Walter Leipold , George Maxim , Marcus Granger-Jones , Nadim Khlat , Baker Scott
IPC: H03H7/46
CPC classification number: H03H7/463 , H01F17/0006
Abstract: RF multiplexer circuitry includes a first signal path coupled between a first intermediate node and a common node, a second signal path coupled between a second intermediate node and the common node, first resonator circuitry coupled between the first signal path and ground, and second resonator circuitry coupled between the second signal path and ground. The first resonator circuitry is configured to allow signals within a first frequency pass band to pass between the first intermediate node and the common node, while attenuating signals outside of the first frequency pass band. The first resonator circuitry includes a first LC resonator. The second resonator circuitry is configured to allow signals within a second frequency pass band to pass between the second intermediate node and the common node, while attenuating signals outside of the second frequency pass band.
Abstract translation: RF多路复用器电路包括耦合在第一中间节点和公共节点之间的第一信号路径，耦合在第二中间节点和公共节点之间的第二信号路径，耦合在第一信号路径和地之间的第一谐振器电路和第二谐振器电路 耦合在第二信号路径和地之间。 第一谐振器电路被配置为允许在第一频率通带内的信号在第一中间节点和公共节点之间通过，同时衰减第一频率通带之外的信号。 第一谐振器电路包括第一LC谐振器。 第二谐振器电路被配置为允许在第二频带内的信号在第二中间节点和公共节点之间通过，同时衰减第二频带之外的信号。
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公开(公告)号：US20160126906A1
公开(公告)日：2016-05-05
申请号：US14931448
申请日：2015-11-03
Applicant: RF Micro Devices, Inc.
Inventor： George Maxim , Dirk Robert Walter Leipold , Baker Scott , Ralph Christopher Nieri
CPC classification number: H03F3/193 , H03F1/0261 , H03F1/223 , H03F1/26 , H03F2200/294 , H03F2200/451 , H03F2200/492 , H04B1/1036 , H04B7/08 , H04B2001/1063 , H04W72/04
Abstract: Circuitry includes a floating-body main field-effect transistor (FET) device, a body-contacted cascode FET device, and biasing circuitry coupled to the floating-body main FET device and the body-contacted cascode FET device. The floating-body main FET device includes a gate contact, a drain contact, and a source contact. The body-contacted cascode FET device includes a gate contact, a drain contact coupled to a supply voltage, and a source contact coupled to the drain contact of the floating-body main FET device and to a body region of the body-contacted cascode FET device. The biasing circuitry is coupled to the gate contact of the floating-body main FET device and the gate contact of the body-contacted cascode FET device and configured to provide biasing signals to the floating-body main FET device and the body-contacted cascode FET device such that a majority of the supply voltage is provided across the body-contacted cascode FET device.
Abstract translation: 电路包括浮体主场效应晶体管（FET）器件，体接触共源共栅FET器件和耦合到浮体主FET器件和体接触共源共栅FET器件的偏置电路。 浮体主FET器件包括栅极接触，漏极接触和源极接触。 身体接触的共源共栅型FET器件包括栅极接触，耦合到电源电压的漏极接触以及耦合到浮体主FET器件的漏极接触和与身体接触的共源共栅FET的体区的源极接触 设备。 偏置电路耦合到浮体主FET器件的栅极接触和体接触共源共栅FET器件的栅极接触，并且被配置为向浮体主FET器件和体接触的共源共栅FET提供偏置信号 器件，使得大部分电源电压被提供在身体接触的共源共栅型FET器件上。
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公开(公告)号：US20160126623A1
公开(公告)日：2016-05-05
申请号：US14931720
申请日：2015-11-03
Applicant: RF Micro Devices, Inc.
Inventor： George Maxim , Dirk Robert Walter Leipold , Marcus Granger-Jones , Baker Scott
IPC: H01Q1/50
CPC classification number: H01L23/315 , H01L21/02266 , H01L21/02282 , H01L21/304 , H01L21/30604 , H01L21/565 , H01L21/6835 , H01L23/20 , H01L23/291 , H01L23/293 , H01L23/3121 , H01L23/3135 , H01L23/36 , H01L23/367 , H01L23/3731 , H01L23/3737 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/562 , H01L24/17 , H01L28/10 , H01L28/20 , H01L28/40 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/92125 , H01L2924/0002 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01Q1/50 , H05K1/0203 , H05K1/181 , H01L2924/00 , H01L2924/014 , H01L2924/00014
Abstract: Antenna aperture tuning circuitry includes a first signal path and a second signal path coupled in parallel between an antenna radiating element and ground. A first LC resonator and a second LC resonator are each coupled between the first signal path and ground. The first LC resonator and the second LC resonator are electromagnetically coupled such that a coupling factor between the first LC resonator and the second LC resonator is between about 1.0% and 40.0%. A third LC resonator and a fourth LC resonator are each coupled between the second signal path and ground. The third LC resonator and the fourth LC resonator are electromagnetically coupled such that a coupling factor between the third LC resonator and the fourth LC resonator is between about 1.0% and 40.0%.
Abstract translation: 天线孔径调谐电路包括在天线辐射元件和地之间并联耦合的第一信号路径和第二信号路径。 第一LC谐振器和第二LC谐振器各自耦合在第一信号路径和地之间。 第一LC谐振器和第二LC谐振器被电磁耦合，使得第一LC谐振器和第二LC谐振器之间的耦合因子在约1.0％和40.0％之间。 第三LC谐振器和第四LC谐振器各自耦合在第二信号路径和地之间。 第三LC谐振器和第四LC谐振器被电磁耦合，使得第三LC谐振器和第四LC谐振器之间的耦合因子在约1.0％和40.0％之间。
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公开(公告)号：US20160126613A1
公开(公告)日：2016-05-05
申请号：US14931689
申请日：2015-11-03
Applicant: RF Micro Devices, Inc.
Inventor： Dirk Robert Walter Leipold , George Maxim , Baker Scott
CPC classification number: H01F27/2804 , H01F2027/2809 , H01L21/0276 , H01L28/10 , H01P7/06 , H01P7/065 , H01P7/08 , H03H7/38 , H03H7/463 , H03H9/24 , H04B1/40 , H04J1/08
Abstract: A resonator includes an inductive element and a conductive cavity surrounding the inductive element. In particular, the conductive cavity surrounds the inductive element such that a capacitance is distributed between the inductive element and the conductive cavity. By distributing a capacitance between the inductive element and the conductive cavity, a high quality-factor resonator can be achieved by the resonator with a relatively small form factor.
Abstract translation: 谐振器包括感应元件和围绕感应元件的导电腔。 特别地，导电腔围绕感应元件，使得电容分布在感应元件和导电腔之间。 通过在电感元件和导电腔之间分配电容，可以通过具有相对小的形状因子的谐振器来实现高质量因子谐振器。
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