公开(公告)号：US06160299A

公开(公告)日：2000-12-12

申请号：US140036

申请日：1998-08-26

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/336 ,  H01L29/78 ,  H01L31/119

CPC classification number: H01L29/6659 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

Abstract: A structure having shallow-implanted elevated source/drain regions is formed with doped sidewall spacers. Diffusion of dopants from the sidewall spacers forms a doped region extending from underneath the gate electrode, along the edge of the epitaxial layer, to the doped (and uppermost) regions of the elevated source/drain. Low junction capacitance, is achieved because the shallow implant of the elevated source/drain regions places the junction inside the source/drain region itself. Low source/drain resistance is achieved because the diffused doped region provides a doped path between the shallow implanted region of the elevated source/drain and the channel region. Low source/drain junction depth is achieved because a second spacer can prevent dopant from being implanted through any faceted areas of the epitaxial layer. The doped extensions of the source/drain regions also have exceptionally low junction depth. The overall process is simpler because it is independent of both facet angle and height of the epitaxial layer.

公开(公告)号：US6127233A

公开(公告)日：2000-10-03

申请号：US205346

申请日：1998-12-03

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/66628 ,  H01L21/28114 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66537

Abstract: A lateral MOSFET (100) and a method for making the same. A two layer raised source/drain region (106) is located adjacent a gate structure (112). The first layer (106a) of the raised source drain is initially doped p-type and the second layer (106b) of the raised source/drain region is doped n-type. P-type dopants from first layer (106a) are diffused into the substrate to form a pocket barrier region (105). N-type dopants from second layer (106b) diffuse into first layer (106a) so that it becomes n-type and into the substrate to form source/drain junction regions (104). P-type pocket barrier region (105) thus provides a barrier between the source/drain junction regions (104) and the channel region (108).

Abstract translation: 横向MOSFET（100）及其制造方法。 两层隆起的源极/漏极区（106）位于栅极结构（112）附近。 凸起的源极漏极的第一层（106a）最初是掺杂p型的，凸起的源极/漏极区的第二层（106b）被掺杂为n型。 来自第一层（106a）的P型掺杂剂扩散到衬底中以形成袋状阻挡区（105）。 来自第二层（106b）的N型掺杂剂扩散到第一层（106a）中，使得其变为n型并进入衬底以形成源极/漏极结区（104）。 因此，P型袋状阻挡区域（105）在源极/漏极结区域（104）和沟道区域（108）之间提供阻挡层。

公开(公告)号：US5793083A

公开(公告)日：1998-08-11

申请号：US755924

申请日：1996-11-25

Applicant: E. Ajith Amerasekera ,  Vincent M. McNeil ,  Mark S. Rodder

Inventor： E. Ajith Amerasekera ,  Vincent M. McNeil ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/08 ,  H01L29/45 ,  H01L29/739 ,  H01L23/62

CPC classification number: H01L27/0266 ,  H01L29/0847 ,  H01L29/7393 ,  H01L29/456

Abstract: A technique for providing a design window for scaled technologies in which good electrostatic discharge/electrical over stress damage and optimum transistor operation can be achieved without the use of additional masks or design steps. The M, beta, and R.sub.sub parameters of the NMOS transistor 13 and associated parasitic npn transistor 10 are selected to provide the design window.

Abstract translation: 提供一种用于缩放技术的设计窗口的技术，其中可以在不使用附加掩模或设计步骤的情况下实现良好的静电放电/电过应力损坏和最佳晶体管操作。 选择NMOS晶体管13和相关联的寄生npn晶体管10的M，β和Rsub参数以提供设计窗口。

公开(公告)号：US5324961A

公开(公告)日：1994-06-28

申请号：US124371

申请日：1993-09-20

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: G11C11/412 ,  H01L27/11

CPC classification number: H01L27/1104 ,  G11C11/4125 ,  Y10S257/904

Abstract: This is an SRAM cell and the cell can comprise: two NMOS drive transistors; two PMOS load transistors; first and second bottom capacitor plates 50,52, with the first plate 50 being over a gate 34 of one of the drive transistors and the second plate 52 being over a gate 40 of another of the drive transistors; a layer of dielectric material 68 over the first and second bottom capacitor plates; and first and second top capacitor plates 20, 26 , over the dielectric layer, with the first top capacitor 20 plate forming a gate of one of the load transistors and with the second top capacitor plate 26 forming a gate of another of the load transistors whereby the capacitor plates form two cross-coupled capacitors between the gates of the drive transistors and the stability of the cell is enhanced. This is also a method of forming an SRAM cell.

Abstract translation: 这是一个SRAM单元，单元可以包括：两个NMOS驱动晶体管; 两个PMOS负载晶体管; 第一和第二底部电容器板50,52，其中第一板50在驱动晶体管之一的栅极34之上，第二板52位于另一个驱动晶体管的栅极40之上; 在第一和第二底部电容器板上的电介质材料层68; 以及第一和第二顶部电容器板20,26，其中第一顶部电容器20板形成负载晶体管中的一个的栅极，并且第二顶部电容器板26形成另一个负载晶体管的栅极，由此 电容器板在驱动晶体管的栅极之间形成两个交叉耦合的电容器，并且增强了电池的稳定性。 这也是形成SRAM单元的方法。

公开(公告)号：US5108935A

公开(公告)日：1992-04-28

申请号：US614775

申请日：1990-11-16

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/336 ,  H01L29/167

CPC classification number: H01L29/66659 ,  H01L29/167 ,  Y10S438/918

Abstract: This invention discloses a method for reducing hot carriers in a transistor structure by means of increasing the scattering rate of the carriers. The increased scattering rate is accomplished by introducing scattering sites comprising of non-conventional dopants, an element which is not boron, phosphorous, or arsenic, into the base or channel region of a transistor.

Abstract translation: 本发明公开了一种通过增加载流子的散射速度来减少晶体管结构中的热载流子的方法。 增加的散射率通过将包含非常规掺杂剂的散射位置（不是硼，磷或砷的元素）引入晶体管的基极或沟道区来实现。

公开(公告)号：US5106777A

公开(公告)日：1992-04-21

申请号：US413038

申请日：1989-09-27

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/763

CPC classification number: H01L21/763

Abstract: A method of forming a trench in a semiconductor body is disclosed herein. A field oxide 16 is grown over a portion of n-well 8 where trench 26 is to be formed. Nitride layer 20 and TEOS oxide layer 22 are deposited. Resist 24 is patterned and TEOS layer 22, nitride layer 20, and field oxide layer 16 are etched. Resist 24 is removed and trench 26 is etched through n-well 8 and into substrate 4. Thin oxide 28 is then grown on the sidewalls of trench 26. Polysilicon is deposited into trench 26 and etched back to form polysilicon plug 30 . Sidewall oxide 32, to prevent voids in the topography of trench 26, is formed on top of polysilicon plug 30 along the outer edges of trench 26. To prevent leakage into trench 26, a thick thermal oxide cap 34 is grown over trench 26.

Abstract translation: 本文公开了一种在半导体本体中形成沟槽的方法。 在要形成沟槽26的n阱8的一部分上生长场氧化物16。 氮化物层20和TEOS氧化物层22沉积。 抗蚀剂24被图案化，TEOS层22，氮化物层20和场氧化物层16被蚀刻。 去除抗蚀剂24，并且通过n阱8蚀刻沟槽26并进入衬底4.然后在沟槽26的侧壁上生长薄氧化物28.多晶硅沉积到沟槽26中并回蚀以形成多晶硅插塞30。 沿着沟槽26的外缘在多晶硅插塞30的顶部形成侧壁氧化物32，以防止沟槽26的形貌中的空隙。为了防止泄漏到沟槽26中，在沟槽26上生长厚的热氧化物帽34。

公开(公告)号：US5087581A

公开(公告)日：1992-02-11

申请号：US606674

申请日：1990-10-31

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/7827 ,  H01L29/1033 ,  H01L29/66666 ,  H01L29/4236

Abstract: This is a vertical MOSFET device with low gate to source overlap capacitance. It can comprise a semiconductor substrate 22 of the first conductivity type, a source region 24, 26 of a second conductivity type formed in the upper surface of the substrate 22; a vertical pillar with a channel region 28 of the first conductivity type, a lightly doped drain region 30 of the second conductivity type and a highly doped drain contact region 32 of the second conductivity type; a gate insulator 34, a gate electrode 36 surrounding the vertical pillar, and an insulating spacer 38 between the source 24, 26 and a portion of the gate 36 regions. This is also a method of forming a vertical MOSFET device on a single crystal semiconductor substrate, with the device having a pillar on the substrate, with the pillar having a channel region in a lower portion and with the channel region having a top and a highly doped first source/drain region in an upper portion of the pillar, with the substrate having a highly doped second source/drain region and with a gate insulator on the substrate and on the pillar. The method comprises: isotropically forming a first gate electrode material layer on the pillar and the substrate; anisotropically etching the first gate electrode material leaving a vertical portion of gate electrode material on the pillar; anisotropically depositing an insulating spacer; and conformally depositing a second gate electrode material layer.

Abstract translation: 这是具有低栅极到源极重叠电容的垂直MOSFET器件。 它可以包括第一导电类型的半导体衬底22，形成在衬底22的上表面中的第二导电类型的源区24,26; 具有第一导电类型的沟道区28的垂直柱，第二导电类型的轻掺杂漏极区30和第二导电类型的高掺杂漏极接触区32; 栅极绝缘体34，围绕垂直柱的栅电极36以及源24,26与栅极36区域的一部分之间的绝缘间隔物38。 这也是在单晶半导体衬底上形成垂直MOSFET器件的方法，其中该器件在衬底上具有一个柱，其中该柱在下部具有沟道区，并且沟道区具有顶部和高度 掺杂的第一源极/漏极区域，其中衬底具有高度掺杂的第二源极/漏极区域，并且在衬底上和栅极上具有栅极绝缘体。 该方法包括：在柱和衬底上各向同性地形成第一栅电极材料层; 各向异性地蚀刻第一栅电极材料，留下柱上的栅电极材料的垂直部分; 各向异性沉积绝缘垫片; 并保形地沉积第二栅电极材料层。

公开(公告)号：US5073519A

公开(公告)日：1991-12-17

申请号：US607011

申请日：1990-10-31

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L29/7827 ,  H01L29/7834

Abstract: This is a vertical MOSFET device with low gate to drain overlap capacitance. It can comprise a semiconductor substrate 22 of the first conductivity type, a source region 24,26 of a second conductivity type formed in the upper surface of the substrate 22; a vertical pillar with a channel region 28 of the first conductivity type, a lightly doped drain region 30 of the second conductivity type and a highly doped drain contact region 32 of the second conductivity type; a gate insulator 34, and a gate electrode 36 surrounding the vertical pillar not substantially extending into the highly doped drain contact region 30. This is also a method of forming a vertical MOSFET device on a single crystal semiconductor substrate, the device having a pillar on the substrate, with the pillar having a channel region in a lower portion and with the channel region having a top and a highly doped first source/drain region in an upper portion of the pillar, with the substrate having a highly doped second source/drain region and with a gate insulator on the substrate and on the pillar. The method comprises: isotropically forming a gate electrode material layer on the pillar and the substrate; anisotropically depositing a gate height determining insulator material on horizontal surfaces to at least the top of the channel region but not substantially overlapping the first highly doped source/drain region; and etching exposed gate electrode material to remove exposed gate electrode material above the gate height determining insulator material.

Abstract translation: 这是具有低栅极到漏极重叠电容的垂直MOSFET器件。 它可以包括第一导电类型的半导体衬底22，形成在衬底22的上表面中的第二导电类型的源区24,26; 具有第一导电类型的沟道区28的垂直柱，第二导电类型的轻掺杂漏极区30和第二导电类型的高掺杂漏极接触区32; 栅极绝缘体34和围绕垂直柱的栅电极36，其基本上不延伸到高掺杂漏极接触区域30.这也是在单晶半导体衬底上形成垂直MOSFET器件的方法，该器件具有柱 该衬底具有在下部中的沟道区，并且该沟道区在该柱的上部具有顶部和高度掺杂的第一源极/漏极区，衬底具有高度掺杂的第二源极/漏极 并且在衬底和柱上具有栅极绝缘体。 该方法包括：在柱和衬底上各向同性地形成栅电极材料层; 将水平表面上的栅极高度确定绝缘体材料各向异性沉积到至少沟道区域的顶部，但基本上不与第一高掺杂源极/漏极区域重叠; 并蚀刻暴露的栅电极材料以去除栅极高度确定绝缘体材料上方的暴露的栅电极材料。

公开(公告)号：US20150093868A1

公开(公告)日：2015-04-02

申请号：US14489965

申请日：2014-09-18

Applicant: Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

Inventor： Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L29/161 ,  H01L29/165 ,  H01L21/308 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: Integrated circuit devices including fin field-effect transistors (finFETs) and methods of forming the same are provided. The methods may include forming a fin-shaped channel region including germanium on a substrate and forming a source/drain region adjacent the channel region on the substrate. The methods may further include forming a barrier layer contacting sidewalls of the channel region and the source/drain region, and the barrier layer may include SixGe1-x, and x may be in a range of about 0.05 to about 0.2.

Abstract translation: 提供包括鳍状场效应晶体管（finFET）的集成电路器件及其形成方法。 所述方法可以包括在衬底上形成包括锗的鳍状沟道区，并形成与衬底上的沟道区相邻的源极/漏极区。 所述方法还可以包括形成与沟道区域和源极/漏极区域的侧壁接触的阻挡层，并且阻挡层可以包括SixGe1-x，x可以在约0.05至约0.2的范围内。

公开(公告)号：US07560779B2

公开(公告)日：2009-07-14

申请号：US10426454

申请日：2003-04-29

Applicant: Mark S. Rodder ,  Jarvis B. Jacobs

Inventor： Mark S. Rodder ,  Jarvis B. Jacobs

IPC: H01L27/088

CPC classification number: H01L21/823857 ,  H01L21/823814

Abstract: A mixed voltage circuit is formed by providing a substrate (12) having a first region (20) for forming a first device (106), a second region (22) for forming a second device (108) complementary to the first device (106), and a third region (24) for forming a third device (110) that operates at a different voltage than the first device (106). A gate layer (50) is formed outwardly of the first, second, and third regions (20, 22, 24). While maintaining a substantially uniform concentration of a dopant type (51) in the gate layer (50), a first gate electrode (56) is formed in the first region (20), a second gate electrode (58) is formed in the second region (22), and a third gate electrode (60) is formed in the third region (24). The third region (24) is protected while implanting dopants (72) into the first region (20) to form source and drain features (74) for the first device (106). The first region (20) is protected while implanting dopants (82) into the third region (24) to form disparate source and drain features (84) for the third device (110).

Abstract translation: 通过提供具有用于形成第一装置（106）的第一区域（20）的基板（12），形成与第一装置（106）互补的第二装置（108）的第二区域（22）形成混合电压电路 ）和用于形成在与第一装置（106）不同的电压下工作的第三装置（110）的第三区域（24）。 栅极层（50）形成在第一，第二和第三区域（20,22,24）的外侧。 在栅极层（50）中保持掺杂剂类型（51）的浓度基本均匀的同时，在第一区域（20）中形成第一栅电极（56），第二栅电极（58）形成在第二栅极 区域（22）和第三栅电极（60）形成在第三区域（24）中。 第三区域（24）被保护，同时将掺杂剂（72）注入到第一区域（20）中以形成用于第一装置（106）的源极和漏极特征（74）。 第一区域（20）被保护，同时将掺杂剂（82）注入到第三区域（24）中以形成用于第三装置（110）的不同的源极和漏极特征（84）。