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    SEMICONDUCTOR DEVICE
    42.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20170012138A1

    公开(公告)日：2017-01-12

    申请号：US15270064

    申请日：2016-09-20

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hideomi SUZAWA ,  Tetsuhiro TANAKA ,  Yuhei SATO ,  Sachiaki TEZUKA ,  Shunpei YAMAZAKI

    IPC: H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

    CPC classification number: H01L29/78648 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/41733 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2029/42388

    Abstract: A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having small current in an off state (in a non-conductive state) is provided. A semiconductor device including such a transistor is provided. A first electrode is formed over a substrate, a first insulating layer is formed adjacent to a side surface of the first electrode, and a second insulating layer is formed to cover the first insulating layer and be in contact with at least part of a surface of the first electrode. The surface of the first electrode is formed of a conductive material that does not easily transmit an impurity element. The second insulating layer is formed of an insulating material that does not easily transmit an impurity element. An oxide semiconductor layer is formed over the first electrode with a third insulating layer provided therebetween.

    Abstract translation: 提供具有高场效应迁移率的晶体管。 提供具有稳定电特性的晶体管。 提供了处于断开状态（非导通状态）的小电流的晶体管。 提供了包括这种晶体管的半导体器件。 第一电极形成在衬底上，第一绝缘层与第一电极的侧表面相邻地形成，并且形成第二绝缘层以覆盖第一绝缘层并与第一绝缘层的至少一部分表面接触 第一个电极。 第一电极的表面由不容易透过杂质元素的导电材料形成。 第二绝缘层由不容易透过杂质元素的绝缘材料形成。 在第一电极上形成氧化物半导体层，其间设置有第三绝缘层。

    SEMICONDUCTOR DEVICE
    43.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20160247935A1

    公开(公告)日：2016-08-25

    申请号：US15145896

    申请日：2016-05-04

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Yutaka OKAZAKI

    IPC: H01L29/786 ,  H01L27/105 ,  H01L29/66

    CPC classification number: H01L29/78606 ,  H01L27/1052 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

    Abstract: To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer filling a groove is surrounded by insulating layers including an aluminum oxide film containing excess oxygen. Excess oxygen contained in the aluminum oxide film is supplied to the oxide semiconductor layer, in which a channel is formed, by heat treatment in a manufacturing process of the semiconductor device. Moreover, the aluminum oxide film forms a barrier against oxygen and hydrogen, which inhibits the removal of oxygen from the oxide semiconductor layer surrounded by the insulating layers including an aluminum oxide film and the entry of impurities such as hydrogen in the oxide semiconductor layer. Thus, a highly purified intrinsic oxide semiconductor layer can be obtained. The threshold voltage is controlled effectively by gate electrode layers formed over and under the oxide semiconductor layer.

    Abstract translation: 提供一种包含氧化物半导体并在保持良好的电气性能的同时小型化的半导体器件。 在半导体器件中，填充沟槽的氧化物半导体层由包含过量氧的氧化铝膜的绝缘层包围。 通过在半导体器件的制造工艺中的热处理，将氧化铝膜中含有的过量氧供给到形成有沟道的氧化物半导体层。 此外，氧化铝膜形成阻止氧和氢的阻挡，其阻止氧化物从包括氧化铝膜的绝缘层包围的氧化物半导体层中除去，并且在氧化物半导体层中进入诸如氢的杂质。 因此，可以获得高度纯化的本征氧化物半导体层。 通过在氧化物半导体层上形成的栅电极层有效地控制阈值电压。

    SEMICONDUCTOR DEVICE
    44.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20160240690A1

    公开(公告)日：2016-08-18

    申请号：US15137621

    申请日：2016-04-25

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Tetsuhiro TANAKA

    IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49

    CPC classification number: H01L29/78693 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02581 ,  H01L21/02617 ,  H01L21/02631 ,  H01L21/32139 ,  H01L27/1225 ,  H01L29/26 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78 ,  H01L29/78606 ,  H01L29/7869

    Abstract: A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device includes an oxide semiconductor layer in a channel formation region, and by the use of an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer, oxygen of the oxide insulating film or the gate insulating film is supplied to the oxide semiconductor layer. Further, a conductive nitride is used for a metal film of a source electrode layer and a drain electrode layer, whereby diffusion of oxygen to the metal film is suppressed.

    Abstract translation: 提供了可以抑制氧化物半导体层中氧空位增加的半导体器件。 提供了具有良好电气特性的半导体器件。 提供了一种高度可靠的半导体器件。 半导体器件包括在沟道形成区域中的氧化物半导体层，并且通过使用氧化物半导体层下方并与氧化物半导体层接触的氧化物绝缘膜和与氧化物半导体层接触的栅绝缘膜， 氧化物绝缘膜或栅极绝缘膜被提供给氧化物半导体层。 此外，导电氮化物用于源电极层和漏电极层的金属膜，从而抑制氧向金属膜的扩散。

    SEMICONDUCTOR DEVICE
    45.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20160079432A1

    公开(公告)日：2016-03-17

    申请号：US14942354

    申请日：2015-11-16

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Yutaka OKAZAKI

    IPC: H01L29/786

    CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696

    Abstract: To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer is surrounded by an insulating layer including an aluminum oxide film containing excess oxygen. Excess oxygen in the aluminum oxide film is supplied to the oxide semiconductor layer including a channel by heat treatment in a manufacturing process of the semiconductor device. Furthermore, the aluminum oxide film forms a barrier against oxygen and hydrogen. It is thus possible to suppress the removal of oxygen from the oxide semiconductor layer surrounded by the insulating layer including an aluminum oxide film, and the entry of impurities such as hydrogen into the oxide semiconductor layer; as a result, the oxide semiconductor layer can be made highly intrinsic. In addition, gate electrode layers over and under the oxide semiconductor layer control the threshold voltage effectively.

    Abstract translation: 提供一种包含氧化物半导体并在保持良好的电气性能的同时小型化的半导体器件。 在半导体器件中，氧化物半导体层被包含含有过量氧的氧化铝膜的绝缘层包围。 在半导体器件的制造工艺中，通过热处理将氧化铝膜中的氧过多地供给到包括沟道的氧化物半导体层。 此外，氧化铝膜形成对氧和氢的阻挡。 因此，可以抑制由包含氧化铝膜的绝缘层包围的氧化物半导体层中的氧的除去以及诸如氢的杂质进入到氧化物半导体层中的氧; 结果，可以使氧化物半导体层高度固有。 此外，氧化物半导体层上方和下方的栅电极层有效地控制阈值电压。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    46.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20150137124A1

    公开(公告)日：2015-05-21

    申请号：US14609814

    申请日：2015-01-30

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yuji EGI ,  Hideomi SUZAWA ,  Shinya SASAGAWA

    IPC: H01L29/786 ,  H01L29/06

    CPC classification number: H01L29/7869 ,  H01L21/0206 ,  H01L21/02565 ,  H01L21/44 ,  H01L21/465 ,  H01L21/4757 ,  H01L21/47635 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/14616 ,  H01L29/045 ,  H01L29/0684 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78693

    Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.

    Abstract translation: 在包括其中设置有侧壁绝缘层的侧表面上的氧化物半导体层，栅极绝缘层和栅电极层的晶体管的半导体器件中，依次层叠源电极层和漏电极层 提供与氧化物半导体层和侧壁绝缘层接触。 在制造半导体器件的方法中，层叠导电层和层间绝缘层以覆盖氧化物半导体层，侧壁绝缘层和栅极电极层。 然后，通过化学机械抛光方法去除层间绝缘层和栅电极层上的导电层的部分，从而形成源电极层和漏电极层。 在形成栅绝缘层之前，对氧化物半导体层进行清洗处理。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    47.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
    半导体器件及制造半导体器件的方法

    公开(公告)号：US20150069387A1

    公开(公告)日：2015-03-12

    申请号：US14479623

    申请日：2014-09-08

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA ,  Yasuhiko TAKEMURA

    IPC: H01L29/786 ,  H01L29/66

    CPC classification number: H01L29/7869 ,  G11C11/24 ,  G11C16/00 ,  G11C16/0466 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/7881

    Abstract: A method for manufacturing a semiconductor device with adjusted threshold is provided. In a semiconductor device including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is provided, a charge trap layer provided between the first gate electrode and the semiconductor, and a gate insulating layer provided between the second gate electrode and the semiconductor, a threshold is increased by trapping electrons in the charge trap layer by keeping a potential of the first gate electrode at a potential higher than a potential of the source or drain electrode for 1 second or more while heating. After the threshold adjustment process, the first gate electrode is removed or insulated from other circuits. Alternatively, a resistor may be provided between the first gate electrode and other circuits.

    Abstract translation: 提供一种用于制造具有调节阈值的半导体器件的方法。 在包括半导体，与半导体电连接的源电极或漏电极的半导体器件中，设置有半导体的第一栅电极和第二栅电极，设置在第一栅电极和半导体之间的电荷陷阱层，以及 设置在第二栅电极和半导体之间的栅极绝缘层，通过将第一栅电极的电位保持在高于源电极或漏电极的电位的电位为1，通过在电荷陷阱层中俘获电子来增加阈值 第二次或多次加热。 在阈值调整处理之后，第一栅电极被去除或与其它电路绝缘。 或者，可以在第一栅极电极和其它电路之间设置电阻器。

    SEMICONDUCTOR DEVICE
    48.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140239293A1

    公开(公告)日：2014-08-28

    申请号：US14174438

    申请日：2014-02-06

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Akihisa SHIMOMURA ,  Tetsuhiro TANAKA ,  Sachiaki TEZUKA

    IPC: H01L29/78 ,  H01L29/26

    CPC classification number: H01L29/7869 ,  H01L29/105 ,  H01L29/26 ,  H01L29/41733 ,  H01L29/78 ,  H01L29/78693 ,  H01L29/78696

    Abstract: Disclosed is a semiconductor device including two oxide semiconductor layers, where one of the oxide semiconductor layers has an n-doped region while the other of the oxide semiconductor layers is substantially i-type. The semiconductor device includes the two oxide semiconductor layers sandwiched between a pair of oxide layers which have a common element included in any of the two oxide semiconductor layers. A double-well structure is formed in a region including the two oxide semiconductor layers and the pair of oxide layers, leading to the formation of a channel formation region in the n-doped region. This structure allows the channel formation region to be surrounded by an i-type oxide semiconductor, which contributes to the production of a semiconductor device that is capable of feeding enormous current.

    Abstract translation: 公开了包括两个氧化物半导体层的半导体器件，其中氧化物半导体层中的一个具有n掺杂区域，而另一个氧化物半导体层基本上是i型。 半导体器件包括夹在一对氧化物层之间的两个氧化物半导体层，其具有包含在两个氧化物半导体层中的任一个中的共同元素。 在包括两个氧化物半导体层和一对氧化物层的区域中形成双阱结构，导致在n掺杂区域中形成沟道形成区域。 该结构允许沟道形成区域被i型氧化物半导体包围，这有助于生产能够馈送大量电流的半导体器件。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    50.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20130161605A1

    公开(公告)日：2013-06-27

    申请号：US13716891

    申请日：2012-12-17

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shinya SASAGAWA ,  Hideomi SUZAWA

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7869 ,  H01L27/1156 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/78606 ,  H01L29/78636 ,  H01L29/78696

    Abstract: A bottom-gate transistor with a short channel length and a method for manufacturing the transistor are provided. A bottom-gate transistor with a short channel length in which portions of a source electrode and a drain electrode which are proximate to a channel formation region are thinner than other portions thereof was devised. In addition, the portions of the source electrode and the drain electrode which are proximate to the channel formation region are formed in a later step than the other portions thereof, whereby a bottom-gate transistor with a short channel length can be manufactured.

    Abstract translation: 提供具有短沟道长度的底栅晶体管和制造晶体管的方法。 设计了具有短沟道长度的底栅晶体管，其中靠近沟道形成区的源电极和漏极的部分比其它部分薄。 此外，靠近沟道形成区域的源电极和漏极的部分以比其它部分稍后的步骤形成，由此可以制造具有短沟道长度的底栅晶体管。

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