中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

57 records (took 0.023 seconds)

    Method for Addressing a Non-Volatile Memory on I2C Bus and Corresponding Memory Device
    44.
    发明申请
    Method for Addressing a Non-Volatile Memory on I2C Bus and Corresponding Memory Device 审中-公开

    公开(公告)号：US20180301196A1

    公开(公告)日：2018-10-18

    申请号：US15842586

    申请日：2017-12-14

    Applicant: STMicroelectronics (Rousset)SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G11C16/20 ,  G06F12/02 ,  G11C16/12 ,  G11C16/10 ,  G11C11/56

    Abstract: Some embodiments include a method for addressing an integrated circuit for a non-volatile memory of the EEPROM type on a bus of the I2C type. The memory includes J hardware-identification pins, with J being an integer lying between 1 and 3, which are assigned respective potentials defining an assignment code on J bits. The method includes a first mode of addressing used selectively when the assignment code is equal to a fixed reference code on J bits, and a second mode of addressing used selectively when the assignment code is different from the reference code. In the first mode, the memory plane of the non-volatile memory is addressed by a memory address contained in the last low-order bits of the slave address and in the first N bytes received. In the second mode, the memory plane is addressed by a memory address contained in the first N+1 bytes received.

    Non-Volatile Memory Device Having a Memory Size
    47.
    发明申请
    Non-Volatile Memory Device Having a Memory Size 有权

    公开(公告)号：US20170090813A1

    公开(公告)日：2017-03-30

    申请号：US15053950

    申请日：2016-02-25

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G06F3/06

    CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0688 ,  G11C5/066 ,  G11C7/10 ,  G11C8/12

    Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.

    Method and system for managing a writing cycle of a data in a EEPROM memory cell
    48.
    发明授权
    Method and system for managing a writing cycle of a data in a EEPROM memory cell 有权
    用于管理EEPROM存储单元中数据写入周期的方法和系统

    公开(公告)号：US09576670B1

    公开(公告)日：2017-02-21

    申请号：US15244521

    申请日：2016-08-23

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/14 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459

    Abstract: An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly.

    Abstract translation: 在电可擦除可编程只读存储器类型的至少一个存储单元中写入至少一个数据的操作包括通过相应的擦除或编程脉冲擦除或编程单元的至少一个步骤。 通过在相应的擦除或编程步骤期间分析擦除或编程脉冲的形式来检查写入操作的正确或不正确的导通。 该分析的结果代表正在进行的写入操作正确或不正确。

    Method and System for Managing a Writing Cycle of a Data in a EEPROM Memory Cell
    49.
    发明申请
    Method and System for Managing a Writing Cycle of a Data in a EEPROM Memory Cell 审中-公开
    用于管理EEPROM存储单元中的数据写入周期的方法和系统

    公开(公告)号：US20170040060A1

    公开(公告)日：2017-02-09

    申请号：US15244521

    申请日：2016-08-23

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30

    CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459

    Abstract: An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly.

    Abstract translation: 用于在电可擦除和可编程只读存储器类型的至少一个存储单元中写入至少一个数据的操作包括通过相应的擦除或编程脉冲擦除或编程单元的至少一个步骤。 通过在相应的擦除或编程步骤期间对擦除或编程脉冲的形式的分析来检查写入操作的正确或不正确的导通。 该分析的结果代表正在进行的写入操作正确或不正确。

    Electronic device with a radiofrequency function
    50.
    发明授权
    Electronic device with a radiofrequency function 有权
    具有射频功能的电子设备

    公开(公告)号：US09544025B2

    公开(公告)日：2017-01-10

    申请号：US14849385

    申请日：2015-09-09

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: H04B5/00 ,  G06K19/077 ,  H02H9/04

    CPC classification number: H04B5/0037 ,  G06K19/07769 ,  H02H9/044

    Abstract: An electronic device includes at least one processing circuit connected through at least one terminal at a first reference voltage. At least one radio frequency communication circuit is connected at least to receive the reference voltage. At least one first pad is intended to be taken to a second reference voltage of at least one electronic circuit external to the device. At least one first resistive impedance is coupled between the terminal and the first pad.

    Abstract translation: 电子设备包括至少一个处理电路，其通过至少一个终端以第一参考电压连接。 至少一个射频通信电路至少连接以接收参考电压。 至少一个第一焊盘旨在被带到设备外部的至少一个电子电路的第二参考电压。 至少一个第一电阻阻抗耦合在端子和第一焊盘之间。

Patent Agency Ranking