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公开(公告)号：US09691493B1
公开(公告)日：2017-06-27
申请号：US15244664
申请日：2016-08-23
Inventor： Marco Pasotti , Fabio De Santis , Roberto Bregoli , Dario Livornesi , Sandor Petenyi
CPC classification number: G11C16/30 , G05F3/30 , G11C5/147 , G11C16/0408 , G11C16/0433 , G11C16/10 , G11C16/28 , G11C2216/10 , H01L27/11521 , H01L27/1156 , H03F3/45188 , H03F3/45475 , H03F2200/456 , H03F2203/45341 , H03F2203/45342 , H03F2203/45528 , H03F2203/45674 , H03F2203/45676
Abstract: A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.
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公开(公告)号：US20170178722A1
公开(公告)日：2017-06-22
申请号：US15422290
申请日：2017-02-01
Inventor： Marco Pasotti , Marcella Carissimi , Rajat Kulshrestha , Chantal AURICCHIO
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C7/065 , G11C7/08 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0061 , G11C13/0097 , G11C2013/0042 , G11C2207/002
Abstract: A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.
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公开(公告)号：US20160099033A1
公开(公告)日：2016-04-07
申请号：US14506865
申请日：2014-10-06
Inventor： Abhishek Lal , Vikas Rana , Marco Pasotti
Abstract: A memory includes a column decoder performing at least two levels of decoding using a first level decoder that decodes between the column bit lines and first level decode lines and a second level decoder that decodes between the first level decode lines and second level decode lines. The second level decoder includes first transistors coupled between the first level decode lines and read output lines and second transistors coupled between the first level decode lines and write input lines. The first transistors have a first voltage rating and are driven by decode control signals referenced to a low supply voltage compatible with the first voltage rating. The second transistors have a second voltage rating, higher than the first voltage rating, and are driven by decode control signals referenced to a high supply voltage (in excess of the low supply voltage) compatible with the second voltage rating.
Abstract translation: 存储器包括列解码器，其使用在列位线和第一电平解码线之间解码的第一电平解码器和在第一电平解码线和第二电平解码线之间解码的第二电平解码器来执行解码的至少两个级别。 第二电平解码器包括耦合在第一电平解码线和读出输出线之间的第一晶体管和耦合在第一电平解码线和写输入线之间的第二晶体管。 第一晶体管具有第一电压额定值，并且由与第一额定电压兼容的低电源电压参考的解码控制信号驱动。 第二晶体管具有高于第一电压额定值的第二电压额定值，并且由与第二额定电压兼容的高电源电压（超过低电源电压）的解码控制信号驱动。
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公开(公告)号：US12211582B2
公开(公告)日：2025-01-28
申请号：US17718755
申请日：2022-04-12
Inventor： Marco Pasotti , Marcella Carissimi , Alessio Antolini , Eleonora Franchi Scarselli , Antonio Gnudi , Andrea Lico
Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A switching circuit is connected between each bit line and a corresponding column output. The switching circuit is controlled to turn on to generate the analog signal dependent on the computational weight and for a time duration controlled by the coefficient data signal. A column combining circuit combines (by addition and/or subtraction) and integrates analog signals at the column outputs of the biasing circuits. The addition/subtraction is dependent on one or more a sign of the coefficient data and a sign of the computational weight and may further implement a binary weighting function.
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公开(公告)号：US12046987B2
公开(公告)日：2024-07-23
申请号：US17582431
申请日：2022-01-24
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Pasotti , Laura Capecchi , Riccardo Zurla , Marcella Carissimi
CPC classification number: H02M1/0045 , G05F1/575 , H02M3/073 , G11C13/0004 , G11C13/0038
Abstract: A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
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Patent Agency Ranking
公开(公告)号：US11894052B2
公开(公告)日：2024-02-06
申请号：US17718908
申请日：2022-04-12
Inventor： Marco Pasotti , Marcella Carissimi , Alessio Antolini , Eleonora Franchi Scarselli , Antonio Gnudi , Andrea Lico , Paolo Romele
CPC classification number: G11C13/0061 , G11C13/0004 , G11C13/0026 , G11C13/0038
Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.
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公开(公告)号：US11615820B1
公开(公告)日：2023-03-28
申请号：US17490976
申请日：2021-09-30
Inventor： Laura Capecchi , Marcella Carissimi , Marco Pasotti , Vikas Rana , Vivek Tyagi
Abstract: A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.
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公开(公告)号：US11424676B2
公开(公告)日：2022-08-23
申请号：US17145107
申请日：2021-01-08
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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49.发明授权公开(公告)号：US11342031B2
公开(公告)日：2022-05-24
申请号：US17006510
申请日：2020-08-28
Inventor： Marco Pasotti , Dario Livornesi , Roberto Bregoli , Vikas Rana , Abhishek Mittal
Abstract: An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.
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公开(公告)号：US20210234460A1
公开(公告)日：2021-07-29
申请号：US17145107
申请日：2021-01-08
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
IPC: H02M3/07
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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