公开(公告)号：US20230020176A1

公开(公告)日：2023-01-19

申请号：US17840819

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeseoung Park ,  Wandon Kim ,  Suyoung Bae ,  Dongsoo Lee ,  Dongsuk Shin ,  Doyoung Choi

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including first and second regions, first and second active patterns provided on the first and second regions, respectively, a pair of first source/drain patterns on the first active pattern and a first channel pattern therebetween, a pair of second source/drain patterns on the second active pattern and a second channel pattern therebetween, first and second gate electrodes respectively provided on the first and second channel patterns, and first and second gate insulating layers respectively interposed between the first and second channel patterns and the first and second gate electrodes. Each of the first and second gate insulating layers includes an interface layer and a first high-k dielectric layer thereon, and the first gate insulating layer further includes a second high-k dielectric layer on the first high-k dielectric layer.

公开(公告)号：US11417656B2

公开(公告)日：2022-08-16

申请号：US16898719

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae Hwang ,  Sunjung Lee ,  Heonbok Lee ,  Geunwoo Kim ,  Wandon Kim

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types from each other; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

公开(公告)号：US20220238539A1

公开(公告)日：2022-07-28

申请号：US17723523

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Musarrat Hasan ,  Wandon Kim ,  Seungkeun Cha

IPC: H01L27/1159 ,  H01L29/78 ,  H01L27/11585 ,  H01L29/51

Abstract: A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel.

公开(公告)号：US20210408260A1

公开(公告)日：2021-12-30

申请号：US17470102

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho Park ,  Byounghoon Lee ,  Seungkeun Cha ,  Wandon Kim

IPC: H01L29/49 ,  H01L29/45 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

Abstract: Semiconductor devices are provided. A semiconductor device includes a first active pattern on a first region of a substrate, a pair of first source/drain patterns on the first active pattern, a first channel pattern between the pair of first source/drain patterns, and a gate electrode that extends across the first channel pattern. The gate electrode is on an uppermost surface and at least one sidewall of the first channel pattern. The gate electrode includes a first metal pattern including a p-type work function metal, a second metal pattern on the first metal pattern and including an n-type work function metal, a first barrier pattern on the second metal pattern and including an amorphous metal layer that includes tungsten (W), carbon (C), and nitrogen (N), and a second barrier pattern on the first barrier pattern. The second barrier pattern includes the p-type work function metal.

公开(公告)号：US09991357B2

公开(公告)日：2018-06-05

申请号：US15186982

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol Song ,  Wandon Kim ,  Hoonjoo Na ,  Suyoung Bae ,  Hyeok-Jun Son ,  Sangjin Hyun

IPC: H01L27/088 ,  H01L29/51 ,  H01L27/085 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.

公开(公告)号：US12230682B2

公开(公告)日：2025-02-18

申请号：US17672033

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoontae Hwang ,  Geunwoo Kim ,  Wandon Kim ,  Hyunbae Lee

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/45

Abstract: An integrated circuit (IC) device includes a conductive region including a first metal on a substrate. An insulating film is on the conductive region. A conductive plug including a second metal passes through the insulating film and extends in a vertical direction. A conductive barrier pattern is between the conductive region and the conductive plug. The conductive barrier pattern has a first surface in contact with the conductive region and a second surface in contact with the conductive plug. A bottom surface and a lower sidewall of the conductive plug are in contact with the conductive barrier pattern, and an upper sidewall of the conductive plug is in contact with the insulating film. The conductive barrier pattern includes a vertical barrier portion between the insulating film and the conductive plug, and the vertical barrier portion has a width tapering along a first direction away from the conductive region.

公开(公告)号：US12021027B2

公开(公告)日：2024-06-25

申请号：US17515954

申请日：2021-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euibok Lee ,  Wandon Kim

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877

Abstract: An integrated circuit (IC) device includes a first conductive line in a closed curve defining a local area on a substrate. The first conductive line has a first end portion and a second end portion. A second conductive line is outside the local area. The second conductive line has a linear line portion along the closed curve and a bulging end portion along the closed curve. The bulging end portion protrudes from the linear line portion toward the first end portion of the first conductive line in the second lateral direction and protrudes further than the first end portion to the outside of the local area. A method of manufacturing an IC device includes forming a first reference pattern having a mandrel hole. A reference spacer is formed inside the mandrel hole. A second reference pattern is formed. The second reference pattern has a shift hole.

公开(公告)号：US11948994B2

公开(公告)日：2024-04-02

申请号：US17531903

申请日：2021-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/3215

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L21/3115 ,  H01L21/3215

Abstract: A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.

公开(公告)号：US11830874B2

公开(公告)日：2023-11-28

申请号：US17578982

申请日：2022-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo Kim ,  Yoon Tae Hwang ,  Wandon Kim ,  Hyunbae Lee

IPC: H01L27/088 ,  H01L29/49 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L23/528 ,  H01L23/5226 ,  H01L29/4941

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

公开(公告)号：US11682706B2

公开(公告)日：2023-06-20

申请号：US17588670

申请日：2022-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Tae Hwang ,  Wandon Kim ,  Geunwoo Kim

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L29/08 ,  H01L21/285 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/41766 ,  H01L21/28518 ,  H01L21/76843 ,  H01L23/53209 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern.