Semiconductor package utilizing a hybrid bonding process and method of manufacturing the same

    公开(公告)号:US11855044B2

    公开(公告)日:2023-12-26

    申请号:US17367005

    申请日:2021-07-02

    Inventor: Jihoon Kim

    CPC classification number: H01L25/0657 H01L23/3107 H01L23/481 H01L2225/06517

    Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a peripheral region having a groove and a bonding region that is disposed higher than the groove. The second semiconductor chip is disposed in the bonding region of the first semiconductor chip. The second semiconductor chip is directly electrically connected to the first semiconductor chip. The second semiconductor chip includes an overhang protruded from the bonding region. The overhang is spaced apart from a bottom surface of the groove. Thus, a bonding failure, which may be caused by particles generated during a cutting the wafer and adhered to the edge portion of the second semiconductor chip, between the first semiconductor chip and the second semiconductor chip might be avoided.

    SEMICONDUCTOR DEVICES
    46.
    发明申请

    公开(公告)号:US20230085456A1

    公开(公告)日:2023-03-16

    申请号:US17859472

    申请日:2022-07-07

    Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate having a groove therein extending in a first direction, a gate insulating layer in the groove, a first conductive pattern in the groove and on the gate insulating layer, and a word line capping pattern in the groove and on the first conductive pattern. The first conductive pattern may include a first material and may include a first conductive portion adjacent to the word line capping pattern and a second conductive portion adjacent to a bottom end of the groove. A largest dimension of a grain of the first material of the first conductive portion may be equal to or larger than that of the first material of the second conductive portion.

    Electronic device and communication device calibration method of electronic device

    公开(公告)号:US11463115B2

    公开(公告)日:2022-10-04

    申请号:US16766105

    申请日:2018-11-23

    Abstract: An electronic device according to various embodiments of the present invention comprises: a housing; a plurality of antennas arranged on or inside the housing; a second communication circuit located inside the housing and electrically connected to the plurality of antennas; a first communication circuit, which is electrically connected to the second communication circuit, and generates a radio frequency (RF) signal or an intermediate frequency (IF) signal so as to transmit the RF or IF signal to the second communication circuit; a memory for storing at least one parameter set to correspond to the characteristic of the second communication circuit; and a control circuit electrically connected to the first communication circuit, wherein the control circuit can be set to transmit a control signal for controlling at least one amplifier included in the second communication circuit to the second communication circuit on the basis of the at least one parameter stored in the memory. Various embodiments of the present invention can be other embodiments.

    Amplifier with post-distortion linearization

    公开(公告)号:US11128265B2

    公开(公告)日:2021-09-21

    申请号:US16734484

    申请日:2020-01-06

    Abstract: A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An amplifier includes a first transistor for amplifying the fundamental signal applied to a gate terminal, and a second transistor having a source terminal electrically connected to the drain terminal of the first transistor and a drain terminal electrically connected to a bias voltage. The current flowing through the second transistor may be determined based on the current flowing in the drain terminal of the first transistor.

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