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41.发明授权公开(公告)号：US08380476B2
公开(公告)日：2013-02-19
申请号：US12568910
申请日：2009-09-29
CPC分类号： G06F17/5036
摘要： Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. To create a model of a small ferroelectric capacitor, a Poisson probability distribution is assigned to each of an array of gridcells defining the probability distribution function of positive and negative coercive voltages, and a number of domains assigned to each gridcell is randomly selected according to that Poisson distribution and an expected number of domains in the modeled capacitor for that gridcell, based on the area of the modeled capacitor. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the superposed polarization of each of the randomly selected domains.
摘要翻译： 包括铁电电容器型号的电子电路仿真。 铁电电容器的模型包括多畴铁电电容器，其中每个畴与正矫顽电压和负矫顽电压相关联。 定义正矫顽电压和负矫顽电压的概率分布函数，从而确定具有矫顽电压的域的分布的加权函数。 为了创建小型铁电电容器的模型，将Poisson概率分布分配给定义正和负矫顽电压的概率分布函数的网格单元阵列中的每一个，并且分配给每个网格单元的域的数量根据该格子随机选择 基于建模电容器的面积，该网格单元的建模电容器的泊松分布和预期数量的域。 通过评估每个随机选择的畴的叠加极化来评估铁电电容器的电性能。
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公开(公告)号：US20120195096A1
公开(公告)日：2012-08-02
申请号：US13445076
申请日：2012-04-12
IPC分类号： G11C11/22
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
摘要翻译： 构建用于可靠性筛选的非易失性锁存电路，例如在存储器单元和触发器中。 非易失性锁存电路各自包括耦合到存储节点的铁电电容器，例如在交叉耦合的反相器的输出端。 单独的板线连接到互补存储节点的铁电电容器。 通过在存储节点设置逻辑状态，然后通过极化将状态编程到铁电电容器中来执行锁存稳定裕度的时间零测试。 掉电后，电路板以相对于彼此的差分电压偏置，然后锁存器上电以尝试调用编程状态。 差分电压会干扰召回，并提供信号余量的测量及其后期寿命的可靠性。
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43.发明申请PASSIVATION OF INTEGRATED CIRCUITS CONTAINING FERROELECTRIC CAPACITORS AND HYDROGEN BARRIERS 有权含有电解电容器和氢气障碍物的集成电路的钝化公开(公告)号：US20120070993A1
公开(公告)日：2012-03-22
申请号：US13303541
申请日：2011-11-23
申请人： Scott R. Summerfelt , Ted S. Moise , Gul B. Basim
发明人： Scott R. Summerfelt , Ted S. Moise , Gul B. Basim
IPC分类号： H01L21/31
CPC分类号： H01L21/3185 , H01L21/0217 , H01L21/76832 , H01L21/76834 , H01L23/5223 , H01L27/11509 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.
摘要翻译： 一种用于形成覆盖铁电电容器和缓冲区域但是从逻辑区域的一部分去除的氢阻挡层的方法。
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公开(公告)号：US08058677B2
公开(公告)日：2011-11-15
申请号：US12396976
申请日：2009-03-03
IPC分类号： H01L23/28
CPC分类号： H01L23/3135 , H01L23/562 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.
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公开(公告)号：US07968974B2
公开(公告)日：2011-06-28
申请号：US12201394
申请日：2008-08-29
IPC分类号： H01L23/02
CPC分类号： H01L23/585 , H01L23/562 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A feedthrough in an IC scribe seal is disclosed. The feedthrough is structured to maintain isolation of components in the IC from mechanical damage and chemical impurities introduced during fabrication and assembly operations. A conductive structure penetrates the scribe seal, possibly in more than one location, connecting an interior region to an exterior region. A feedthrough vertical seal surrounds the conductive element in the IC and connects to the scribe seal. A horizontal diffusion barrier connects to the scribe seal and the feedthrough vertical seal. The feedthrough vertical seal, the horizontal diffusion barrier and the IC substrate form a continuous barrier to chemical impurities around the conductive element in the interior region. The conductive structure includes any combination of a doped region in an active area, an MOS transistor gate layer, and one or more interconnect metal layers. The feedthrough is compatible with aluminum and copper interconnect metallization.
摘要翻译： 公开了IC划片印章中的馈通。 馈通的结构是保持IC中组件的隔离，防止在制造和组装操作过程中引入的机械损伤和化学杂质。 导电结构可能在不止一个位置上穿过划线密封，将内部区域连接到外部区域。 馈通垂直密封件围绕IC中的导电元件并连接到划线密封件。 水平扩散屏障连接到划线密封和馈通垂直密封。 馈通垂直密封件，水平扩散阻挡层和IC基板在内部区域内对导电元件周围的化学杂质形成连续的屏障。 导电结构包括有源区域中的掺杂区域，MOS晶体管栅极层和一个或多个互连金属层的任何组合。 馈通与铝和铜互连金属化兼容。
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公开(公告)号：US07933138B2
公开(公告)日：2011-04-26
申请号：US12362972
申请日：2009-01-30
IPC分类号： G11C11/22
CPC分类号： G11C7/065 , G11C11/22 , G11C2207/063
摘要： A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.
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公开(公告)号：US20110062550A1
公开(公告)日：2011-03-17
申请号：US12718691
申请日：2010-03-05
CPC分类号： H01L21/76843 , H01L27/11509 , H01L28/57
摘要： An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.
摘要翻译： 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。
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公开(公告)号：US20100296329A1
公开(公告)日：2010-11-25
申请号：US12781601
申请日：2010-05-17
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
摘要翻译： 构建用于可靠性筛选的非易失性锁存电路，例如在存储器单元和触发器中。 非易失性锁存电路各自包括耦合到存储节点的铁电电容器，例如在交叉耦合的反相器的输出端。 单独的板线连接到互补存储节点的铁电电容器。 通过在存储节点设置逻辑状态，然后通过极化将状态编程到铁电电容器中来执行锁存稳定裕度的时间零测试。 掉电后，电路板以相对于彼此的差分电压偏置，然后锁存器上电以尝试调用编程状态。 差分电压会干扰召回，并提供信号余量的测量及其后期寿命的可靠性。
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公开(公告)号：US20100041232A1
公开(公告)日：2010-02-18
申请号：US12460602
申请日：2009-07-21
IPC分类号： H01L21/3205 , H01L21/02
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/12 , H01L22/26 , H01L27/0207 , H01L27/11507 , Y02P90/265
摘要： A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).
摘要翻译： 公开了一种在衬底上放置虚拟填充层的方法（图2）。 该方法包括识别衬底（210）的子区域。 确定子区域中的层的密度（212）。 选择虚拟填充层的图案以产生预定的密度（216）。 所选择的图案被放置在子区域（208）中。
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50.发明申请Increasing Exposure Tool Alignment Signal Strength for a Ferroelectric Capacitor Layer 有权增加铁电电容层的曝光工具对准信号强度公开(公告)号：US20090243123A1
公开(公告)日：2009-10-01
申请号：US12411914
申请日：2009-03-26
IPC分类号： H01L23/544 , H01L21/31
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/7084 , H01L2223/54453 , H01L2924/0002 , Y10T29/42 , H01L2924/00
摘要： An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.
摘要翻译： 公开了用于光刻图案对准的改进的对准结构。 在低反射率层下的IC中的地形对准标记可能难以注册。 在低反射层的顶部形成反射层，使得对准标记的形貌在反射层中复制，使得能够使用普通的光刻扫描器和步进器对准对准标记。 反射层可以是一个或多个层，并且可以是金属的，电介质的或两者的。 反射层可以在整个IC上是全局的，或者可以是对准标记区域的局部。 可以在随后的处理期间去除反射层，可能来自添加的蚀刻停止层的辅助，或者可以保留在完整的IC中。 所公开的对准标记结构可应用于具有堆叠铁电电容器材料的IC。
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