公开(公告)号：US09584707B2

公开(公告)日：2017-02-28

申请号：US14935721

申请日：2015-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Yuki Okamoto

IPC: H04N3/14 ,  H04N5/335 ,  H04N5/225 ,  H01L27/146

CPC classification number: H04N5/2253 ,  H01L27/14612 ,  H01L27/14692 ,  H04N5/3696 ,  H04N5/37452 ,  H04N5/378

Abstract: To provide an imaging device capable of obtaining high-quality imaging data. The imaging device includes a first circuit and a second circuit. The first circuit includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and a third capacitor. The second circuit includes an eighth transistor. The imaging device can compensate variation in threshold voltage of an amplifier transistor included in the first circuit.

Abstract translation: 提供能够获得高质量成像数据的成像装置。 成像装置包括第一电路和第二电路。 第一电路包括光电转换元件，第一晶体管，第二晶体管，第三晶体管，第四晶体管，第五晶体管，第六晶体管，第七晶体管，第一电容器，第二电容器和第三电容器。 第二电路包括第八晶体管。 成像装置可以补偿包括在第一电路中的放大器晶体管的阈值电压的变化。

公开(公告)号：US09548327B2

公开(公告)日：2017-01-17

申请号：US14928987

申请日：2015-10-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Yuki Okamoto

IPC: H01L27/14 ,  H01L27/146 ,  H04N5/3745 ,  H04N5/378

CPC classification number: H01L27/14612 ,  H01L27/14643 ,  H01L27/14665 ,  H01L27/14692 ,  H04N5/3696 ,  H04N5/37452 ,  H04N5/37455 ,  H04N5/378

Abstract: To provide an imaging device capable of obtaining high-quality imaging data. The imaging device includes a first circuit and a second circuit. The first circuit includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and a third capacitor. The second circuit includes a seventh transistor. The imaging device can compensate variation in electrical characteristics of an amplifier transistor included in the first circuit.

Abstract translation: 提供能够获得高质量成像数据的成像装置。 成像装置包括第一电路和第二电路。 第一电路包括光电转换元件，第一晶体管，第二晶体管，第三晶体管，第四晶体管，第五晶体管，第六晶体管，第一电容器，第二电容器和第三电容器。 第二电路包括第七晶体管。 成像装置可以补偿包括在第一电路中的放大器晶体管的电特性的变化。

公开(公告)号：US09209795B2

公开(公告)日：2015-12-08

申请号：US14275015

申请日：2014-05-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki Okamoto ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa

IPC: G01R31/26 ,  H03K17/16 ,  G01R19/252

CPC classification number: H03K17/162 ,  G01R19/252 ,  G01R31/2621

Abstract: A signal processing device and a measuring method are provided. A ring oscillator includes (2n+1) signal transmission circuits (n is an integer greater than or equal to 1). One of the signal transmission circuits comprises an inverter, a first transistor, and a second transistor; one of an input terminal and an output terminal of the inverter is connected to one of a source and a drain of the first transistor; one of a source and a drain of the second transistor is connected to a gate of the first transistor; an output of a k-th (k is an integer greater than or equal to 1 and less than or equal to 2n) signal transmission circuit is connected to an input of a (k+1)-th signal transmission circuit; and an output of a (2n+1)-th signal transmission circuit is connected to an input of a first signal transmission circuit.

Abstract translation: 提供信号处理装置和测量方法。 环形振荡器包括（2n + 1）个信号传输电路（n是大于或等于1的整数）。 信号传输电路之一包括反相器，第一晶体管和第二晶体管; 逆变器的输入端子和输出端子之一连接到第一晶体管的源极和漏极之一; 第二晶体管的源极和漏极之一连接到第一晶体管的栅极; 信号发送电路的第k（k为1以上且小于等于2n的整数）的输出连接到第（k + 1）个信号发送电路的输入端; 并且第（2n + 1）个信号传输电路的输出连接到第一信号传输电路的输入端。

公开(公告)号：US20140300403A1

公开(公告)日：2014-10-09

申请号：US14224553

申请日：2014-03-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki Okamoto ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Yasuhiko Takemura

IPC: H03K3/356 ,  H03K3/012 ,  H03F3/45

CPC classification number: H03F3/45076 ,  H03F1/223 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45237 ,  H03F2203/45394 ,  H03F2203/45518 ,  H03F2203/45674 ,  H03K19/018528

Abstract: A level shifter converting a binary signal having a first potential and a second potential into a signal having the first potential and a third potential, and a signal processing circuit using the level shifter are provided. The first potential is higher than the second potential. The second potential is higher than the third potential. The potential difference between the first potential and the third potential may be more than or equal to 3 V and less than 4 V. The level shifter includes a current control circuit which generates a second signal for operating an amplifier circuit for a certain period in accordance with the potential change of the first signal which is input to the amplifier circuit. The output of level shifter is input to a gate of an N-channel transistor whose threshold voltage is lower than 0 V.

Abstract translation: 电平移位器将具有第一电位和第二电位的二进制信号转换为具有第一电位和第三电位的信号，以及使用电平转换器的信号处理电路。 第一个潜力高于第二个潜力。 第二个潜力高于第三个潜力。 第一电位和第三电位之间的电位差可以大于或等于3V且小于4V。电平移位器包括电流控制电路，其产生用于按照一定时间操作放大器电路的第二信号 其中输入到放大器电路的第一信号的电位变化。 电平移位器的输出输入到阈值电压低于0V的N沟道晶体管的栅极。

公开(公告)号：US11990778B2

公开(公告)日：2024-05-21

申请号：US17258957

申请日：2019-06-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki Ikeda ,  Munehiro Kozuma ,  Takanori Matsuzaki ,  Ryota Tajima ,  Shunpei Yamazaki ,  Yuki Okamoto

IPC: H02J7/00 ,  H01M10/42

CPC classification number: H02J7/0031 ,  H01M10/4235 ,  H02J7/0036

Abstract: Safety is secured in such a manner that an anomaly of a secondary battery is detected with a protection circuit, for example, a phenomenon that lowers the safety of a secondary battery, particularly a micro short circuit, is detected early, and users are warned or the use of the secondary battery is stopped. A secondary battery protection circuit includes a first memory circuit electrically connected to a secondary battery, a comparison circuit electrically connected to the first memory circuit, a second memory circuit electrically connected to the comparison circuit, and a power-off switch electrically connected to the second memory circuit. The power-off switch is electrically connected to the secondary battery, and the first memory circuit includes a first transistor including an oxide semiconductor and retains a voltage value of the secondary battery in an analog manner.

公开(公告)号：US11870393B2

公开(公告)日：2024-01-09

申请号：US16868688

申请日：2020-05-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki Okamoto ,  Yoshiyuki Kurokawa

IPC: H03B5/06 ,  H01L27/092 ,  H01L27/12 ,  H03K3/014 ,  H01L29/786 ,  H03K3/03

CPC classification number: H03B5/06 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869 ,  H03K3/014 ,  H03K3/0315

Abstract: An oscillator capable of quick startup is provided. A transistor is provided between an output terminal of a certain stage inverter and an input terminal of the following stage inverter included in the voltage controlled oscillator. With the use of the on resistance of the transistor, the oscillation frequency of the clock signal is controlled. While supply of the power supply voltage is stopped, a signal that is input to the input terminal of the inverter just before supply of the power supply voltage is stopped is stored by turning off the transistor. This operation makes it possible to immediately output a clock signal that has the same frequency as that before supply of the power supply voltage is stopped at the time when the power supply voltage is supplied again.

公开(公告)号：US11823733B2

公开(公告)日：2023-11-21

申请号：US17600379

申请日：2020-04-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi Kunitake ,  Yuto Yakubo ,  Takanori Matsuzaki ,  Yuki Okamoto ,  Tatsuya Onuki

IPC: G11C5/06 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C11/4085 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/789

Abstract: A memory device includes m memory cell blocks, m×(k+1) word lines, n bit lines, and a word line driver circuit (m, k, and n are each an integer greater than or equal to 1). The memory cell block includes memory cells of (k+1) rows×n columns, and each of the memory cells is electrically connected to a word line and a bit line. The word line driver circuit has a function of outputting signals to m×k word lines that are selected from m×(k+1) word lines by using a switch transistor, and selection information is written to a gate of the switch transistor by using a transistor having a low off-state current. The memory cells of k rows×n columns included in the memory cell block are normal memory cells, and each of the memory cell blocks includes redundant memory cells of one row×n columns.

公开(公告)号：US11664786B2

公开(公告)日：2023-05-30

申请号：US17836283

申请日：2022-06-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki Okamoto ,  Kei Takahashi

IPC: H03K5/08 ,  H03K3/0233 ,  H01M10/48 ,  H02J7/02 ,  H03K17/22 ,  H03K19/0185 ,  G06G7/186 ,  H03K19/20

CPC classification number: H03K3/02337 ,  G06G7/186 ,  H01M10/48 ,  H02J7/02 ,  H03K5/084 ,  H03K17/223 ,  H03K19/018557 ,  H03K19/20 ,  H03K2217/96074

Abstract: To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.

公开(公告)号：US11308833B2

公开(公告)日：2022-04-19

申请号：US17014638

申请日：2020-09-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki Okamoto

IPC: G09G3/3233 ,  G09G3/36 ,  G09G3/00 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786

Abstract: An information terminal capable of switching display and non-display of images by strain. The information terminal includes a display portion and a strain sensor. The display portion includes a liquid crystal element, a light-emitting element, and a first and a second transistors. The strain sensor includes a strain sensor element and a resistor. The first transistor has a function of controlling current flowing into the light-emitting element. The strain sensor element has a function as a variable resistor. A first terminal of the strain sensor element is electrically connected to a first terminal of the resistor. A gate of the first transistor is electrically connected to a first terminal of the strain sensor element via the second transistor.

公开(公告)号：US11281285B2

公开(公告)日：2022-03-22

申请号：US16789480

申请日：2020-02-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki Okamoto ,  Yoshiyuki Kurokawa

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/3228 ,  G11C11/412 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/42 ,  G11C11/40 ,  H03K19/0175

Abstract: A method for controlling power supply in a semiconductor device including a CPU and a PLD which can hold data even in an off state is provided. The semiconductor device includes a processor, a programmable logic device, and a state control circuit. The programmable logic device includes a first nonvolatile memory circuit and has a function of holding data obtained by arithmetic processing of the programmable logic device when it is turned off. The state control circuit obtains data on the amount of a task performed by the programmable logic device in accordance with an operation of the processor. The programmable logic device detects the state of progress of the task and outputs a signal to the state control circuit. The state control circuit monitors the amount of the task and the state of progress of the task and turns off the programmable logic device when the task is completed.