公开(公告)号：US09614097B2

公开(公告)日：2017-04-04

申请号：US14280950

申请日：2014-05-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuhiko Takemura ,  Shunpei Yamazaki

IPC: H03K19/17 ,  H01L29/786 ,  H03K19/177 ,  H03K19/173

CPC classification number: H03K19/0013 ,  H01L27/0629 ,  H01L29/7869 ,  H01L2924/0002 ,  H03K17/161 ,  H03K19/173 ,  H03K19/17724 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17772 ,  H03K19/17784 ,  H01L2924/00

Abstract: It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current.

公开(公告)号：US09548395B2

公开(公告)日：2017-01-17

申请号：US14848515

申请日：2015-09-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiromichi Godo ,  Yasuhiko Takemura

IPC: H01L29/12 ,  H01L29/786 ,  H01L27/06 ,  H01L29/78 ,  H01L27/108 ,  H01L27/115 ,  H01L27/12 ,  H01L49/02 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10826 ,  H01L27/10852 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/90 ,  H01L29/41733 ,  H01L29/785 ,  H01L29/78609

Abstract: Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface, a gate insulating film formed to cover the oxide semiconductor, and a gate electrode which is formed to cover the gate insulating film. The gate electrode partly overlaps a source electrode and a drain electrode. The source electrode and the drain electrode are in contact with at least a top surface of the oxide semiconductor. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate electrode, so that electrons injected from the source electrode or the drain electrode can be effectively removed, and most of the space between the source electrode and the drain electrode can be a depletion region; thus, off-state current can be reduced.

Abstract translation: 提供了一种具有小截止电流的场效应晶体管（FET），其用于小型化的半导体集成电路中。 场效应晶体管包括形成为基本上垂直于绝缘表面的薄氧化物半导体，形成为覆盖氧化物半导体的栅极绝缘膜，以及形成为覆盖栅极绝缘膜的栅电极。 栅电极部分地与源电极和漏电极重叠。 源电极和漏极与氧化物半导体的至少顶表面接触。 在这种结构中，薄氧化物半导体的三个表面被栅电极覆盖，使得可以有效地去除从源电极或漏电极注入的电子，源电极和漏电极之间的大部分空间可以是 一个耗尽区域 因此，可以减小截止电流。

公开(公告)号：US09384816B2

公开(公告)日：2016-07-05

申请号：US14474396

申请日：2014-09-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuhiko Takemura

IPC: G11C11/24 ,  G11C11/404 ,  G11C8/14 ,  G11C11/4076 ,  G11C11/408 ,  H01L27/02 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  G11C11/4094

CPC classification number: H01L27/10897 ,  G11C7/02 ,  G11C8/14 ,  G11C11/404 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10805 ,  H01L27/10811 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255

Abstract: In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m_1 or the like). Further, each cell includes selection transistors STr1_n_m and STr2_n_m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2_n_m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.

Abstract translation: 在常规DRAM中，当电容器的电容减小时，容易发生读取数据的错误。 多个单元被连接到一个位线MBL_m。 每个单元包括子位线SBL_n_m和4到64个存储单元（存储单元CL_n_m_1等）。 此外，每个单元包括选择晶体管STr1_n_m和STr2_n_m，作为互补反相器等的放大器电路AMP_n_m连接到选择晶体管STr2_n_m。 由于子位线SBL_n_m的寄生电容足够小，所以每个存储单元的电容器中的电荷引起的电位变化都可以被放大器电路AMP_n_m放大而没有错误，并且可以被输出到位线。

公开(公告)号：US09336858B2

公开(公告)日：2016-05-10

申请号：US14460399

申请日：2014-08-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yasuhiko Takemura

IPC: G11C11/24 ,  G11C11/4096 ,  G11C11/404 ,  G11C16/02 ,  H01L21/28 ,  H01L27/115 ,  H01L27/105 ,  G11C16/04 ,  H01L49/02

CPC classification number: G11C11/4096 ,  G11C11/24 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/1156 ,  H01L28/40

Abstract: A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of a reading transistor and the drain of the writing transistor is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line; a source of the writing transistor is connected to a writing bit line; and a source and a drain of the reading transistor are connected to a reading bit line and a bias line. In order to reduce the number of wirings, the writing bit line or the bias line is substituted for the reading bit line in another column.

公开(公告)号：US09336836B2

公开(公告)日：2016-05-10

申请号：US14559993

申请日：2014-12-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yasuhiko Takemura

IPC: G11C7/02 ,  G11C5/06 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4063

CPC classification number: G11C5/06 ,  G11C7/02 ,  G11C11/4063 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

Abstract: A semiconductor memory device in which capacitance of a capacitor is lower and integration degree is higher. A plurality of memory blocks is connected to one bit line BL_m. A memory block MB_n_m includes a sub bit line SBL_n_m, a write switch, and a plurality of memory cells. A sub bit line SBL_n+1_m adjacent to the sub bit line SBL_n_m is connected to an amplifier circuit AMP_n/n+1_m including two inverters and two selection switches. A circuit configuration of the amplifier circuit can be changed with the selection switches. The amplifier circuit is connected to the bit line BL_m through a read switch. Because of a sufficiently low capacitance of the sub bit line SBL_n_m, potential change due to electric charges of the capacitor in each memory cell can be amplified by the amplifier circuit AMP_n/n+1_m without an error, and the amplified data can be output to the bit line BL_m.

Abstract translation: 一种半导体存储器件，其中电容器的电容较低并且集成度较高。 多个存储块连接到一个位线BL_m。 存储块MB_n_m包括子位线SBL_n_m，写入开关和多个存储器单元。 与子位线SBL_n_m相邻的子位线SBL_n + 1_m连接到包括两个反相器和两个选择开关的放大器电路AMP_n / n + 1_m。 可以通过选择开关来改变放大器电路的电路配置。 放大器电路通过读开关连接到位线BL_m。 由于子位线SBL_n_m的足够低的电容，可以通过放大器电路AMP_n / n + 1_m放大每个存储单元中的电荷引起的电位变化，并且将放大的数据输出到 位线BL_m。

公开(公告)号：US09257422B2

公开(公告)日：2016-02-09

申请号：US13689001

申请日：2012-11-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuhiko Takemura

IPC: H03K17/16 ,  H01L27/06 ,  H03K3/01 ,  H03K3/356 ,  G11C11/403 ,  G11C11/405 ,  G11C19/18 ,  G11C19/28 ,  H01L27/108

CPC classification number: H01L27/06 ,  G11C11/403 ,  G11C11/405 ,  G11C19/184 ,  G11C19/28 ,  H01L27/10852 ,  H03K3/01 ,  H03K3/35606

Abstract: A memory element capable of operating at high speed and reducing power consumption and a signal processing circuit including the memory element are provided. As a writing transistor, a transistor which is formed using an oxide semiconductor and has significantly high off-state resistance is used. In a memory element in which a source of the writing transistor is connected to an input terminal of an inverter, a control terminal of a transfer gate, or the like, the threshold voltage of the writing transistor is lower than a low-level potential. The highest potential of a gate of the writing transistor can be a high-level potential. When the potential of data is the high-level potential, there is no potential difference between a channel and the gate; thus, even when the writing transistor is subsequently turned off, a potential on the source side hardly changes.

Abstract translation: 提供能够高速运行并降低功耗的存储元件和包括存储元件的信号处理电路。 作为写入晶体管，使用使用氧化物半导体形成且具有显着高截止电阻的晶体管。 在写入晶体管的源极连接到反相器的输入端子，传输栅极的控制端子等的存储元件中，写入晶体管的阈值电压低于低电平电位。 写入晶体管的栅极的最高电位可能是一个高层次的潜力。 当数据的电位为高电平时，通道和门之间没有电位差; 因此，即使随后关闭写入晶体管，源极侧的电位几乎不变化。

公开(公告)号：US09112460B2

公开(公告)日：2015-08-18

申请号：US14224553

申请日：2014-03-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki Okamoto ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Yasuhiko Takemura

IPC: H03K3/00 ,  H03F3/45 ,  H03K19/0185 ,  H03F1/22

CPC classification number: H03F3/45076 ,  H03F1/223 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45237 ,  H03F2203/45394 ,  H03F2203/45518 ,  H03F2203/45674 ,  H03K19/018528

Abstract: A level shifter converting a binary signal having a first potential and a second potential into a signal having the first potential and a third potential, and a signal processing circuit using the level shifter are provided. The first potential is higher than the second potential. The second potential is higher than the third potential. The potential difference between the first potential and the third potential may be more than or equal to 3 V and less than 4 V. The level shifter includes a current control circuit which generates a second signal for operating an amplifier circuit for a certain period in accordance with the potential change of the first signal which is input to the amplifier circuit. The output of level shifter is input to a gate of an N-channel transistor whose threshold voltage is lower than 0 V.

Abstract translation: 电平移位器将具有第一电位和第二电位的二进制信号转换为具有第一电位和第三电位的信号，以及使用电平转换器的信号处理电路。 第一个潜力高于第二个潜力。 第二个潜力高于第三个潜力。 第一电位和第三电位之间的电位差可以大于或等于3V且小于4V。电平移位器包括电流控制电路，其产生用于按照一定时间操作放大器电路的第二信号 其中输入到放大器电路的第一信号的电位变化。 电平移位器的输出输入到阈值电压低于0V的N沟道晶体管的栅极。

公开(公告)号：US08975918B2

公开(公告)日：2015-03-10

申请号：US13870039

申请日：2013-04-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuhiko Takemura

IPC: G06F7/38 ,  H03K19/177 ,  G11C7/10 ,  G11C11/24 ,  H03K19/08 ,  H03K19/173

CPC classification number: G11C7/10 ,  G11C11/24 ,  H03K19/08 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/1776

Abstract: To optimize the arrangement of configuration data stored in a configuration memory. A lookup table includes a memory configured to store configuration data, a plurality of multiplexers each configured to select one signal from a plurality of input signals in accordance with the configuration data supplied from the memory and output the one signal, and an inverter. The plurality of multiplexers are connected in a binary tree with multiple levels. The inverter is provided between one of input terminals of a multiplexer in an uppermost level and an output terminal of a multiplexer in one level lower than the uppermost level. Signal selection is performed in each of the multiplexers so that the multiplexer in the uppermost level outputs, as an output signal, one signal of all input signals of the multiplexers in a lowermost level.

公开(公告)号：US20140370184A1

公开(公告)日：2014-12-18

申请号：US14471906

申请日：2014-08-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuhiko Takemura ,  Tamae MORIWAKA

IPC: H01M4/1393 ,  B29B15/00

CPC classification number: H01M4/1393 ,  B29B15/00 ,  H01M4/366 ,  H01M4/60 ,  H01M4/625 ,  H01M4/661 ,  H01M2004/021

Abstract: An object is to increase the conductivity of an electrode including active material particles and the like, which is used for a battery. Two-dimensional carbon including 1 to 10 graphenes is used as a conduction auxiliary agent, instead of a conventionally used conduction auxiliary agent extending only one-dimensionally at most, such as graphite particles, acetylene black, or carbon fibers. A conduction auxiliary agent extending two-dimensionally has higher probability of being in contact with active material particles or other conduction auxiliary agents, so that the conductivity can be improved.

Abstract translation: 目的在于提高用于电池的包含活性物质粒子等的电极的导电性。 使用包含1至10个石墨烯的二维碳作为导电助剂，而不是常规使用的至多一维延伸的导电助剂如石墨颗粒，乙炔黑或碳纤维。 导电辅助剂二维延伸具有与活性材料颗粒或其它导电助剂接触的可能性较高，从而可提高导电性。

公开(公告)号：US20140252353A1

公开(公告)日：2014-09-11

申请号：US14287318

申请日：2014-05-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiromichi Godo ,  Yasuhiko Takemura

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10826 ,  H01L27/10852 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/90 ,  H01L29/41733 ,  H01L29/785 ,  H01L29/78609

Abstract: Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface and has a thickness of greater than or equal to 1 nm and less than or equal to 30 nm, a gate insulating film formed to cover the oxide semiconductor, and a strip-like gate which is formed to cover the gate insulating film and has a width of greater than or equal to 10 nm and less than or equal to 100 nm. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate, so that electrons injected from a source or a drain can be effectively removed, and most of the space between the source and the drain can be a depletion region; thus, off-state current can be reduced.

Abstract translation: 提供了一种具有小截止电流的场效应晶体管（FET），其用于小型化的半导体集成电路中。 场效应晶体管包括形成为基本上垂直于绝缘表面并且具有大于或等于1nm且小于或等于30nm的厚度的薄氧化物半导体，形成为覆盖氧化物半导体的栅极绝缘膜 以及形成为覆盖栅极绝缘膜并且具有大于或等于10nm且小于或等于100nm的宽度的条状栅极。 在这种结构中，薄氧化物半导体的三个表面被栅极覆盖，使得可以有效地去除从源极或漏极注入的电子，并且源极和漏极之间的大部分空间可以是耗尽区; 因此，可以减小截止电流。