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136 条记录 (耗时 0.028 秒)

    Blind body collecting-expanding control device for window blinds
    41.
    发明申请
    Blind body collecting-expanding control device for window blinds 审中-公开
    用于窗帘的盲体收集扩张控制装置

    公开(公告)号：US20070151675A1

    公开(公告)日：2007-07-05

    申请号：US11526064

    申请日：2006-09-25

    申请人： Wu Nien ,  Sheng Hsu ,  Wen Liang

    发明人： Wu Nien ,  Sheng Hsu ,  Wen Liang

    IPC分类号： A47H5/00

    CPC分类号： E06B9/30 ,  E06B9/322 ,  E06B9/62

    摘要： A blind body collecting-expanding control device for window blinds comprises a head rail, a bottom rail, a cord-winding control device, a transmission assembly, and a blind body wherein the head rail has an accommodating channel defining one end thereon to receive the cord-winding control device therein. The cord-winding control device links in movement to the transmission assembly composed of support seats, a winding shaft, lift cords, an operational cord, and a sliding element so that the blind body can be easily actuated thereby to collect upwards or expand downwards in operation. Via the aforementioned structure, the pushing or pulling force exerted by hands reciprocally interacts with the cord-winding control device so that a user can freely adjust the blind body into a desirable position, achieving the best adjustment effect as well as easy and speedy assembly thereof.

    摘要翻译： 用于窗帘的盲体收集扩展控制装置包括头轨，底轨，帘线卷绕控制装置，变速器组件和盲体，其中头轨具有限定其上一端的容纳通道， 帘线卷绕控制装置。 绳索卷绕控制装置连接到由支撑座，卷绕轴，提升绳索，操作绳索和滑动元件组成的传动组件的运动中，使得盲体能够容易地致动从而向上收集或向下收集 操作。 通过上述结构，由手施加的推力或拉力与绳索卷绕控制装置相互作用，使得使用者可以将盲体自由地调节到期望的位置，实现最佳调节效果以及容易且快速地组装 。

    Wide wavelength range silicon electroluminescence device
    43.
    发明申请
    Wide wavelength range silicon electroluminescence device 审中-公开
    宽波长范围的硅电致发光器件

    公开(公告)号：US20060180816A1

    公开(公告)日：2006-08-17

    申请号：US11058505

    申请日：2005-02-14

    申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

    发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

    IPC分类号： H01L29/26

    CPC分类号： H05B33/145

    摘要： A method is provided for forming a Si electroluminescence (EL) device for emitting light at short wavelengths. The method comprises: providing a substrate; forming a first insulator layer overlying the substrate; forming a silicon-rich silicon oxide (SRSO) layer overlying the first insulator layer, embedded with nanocrystalline Si having a size in the range of 0.5 to 5 nm; forming a second insulator layer overlying the SRSO layer; and, forming a top electrode. Typically, the SRSO has a Si richness in the range of 5 to 40%. In one aspect, the SRSO layer is formed using a DC sputtering process. In another aspect, the SRSO formation step includes a rapid thermal annealing (RTA) process subsequent to depositing the SRSO. Likewise, thermal oxidation or plasma oxidation can be performed subsequent to the SRSO layer deposition. The size of Si nanocrystals is decreased in response to above-mentioned deposition, annealing, and oxidation processes.

    摘要翻译： 提供一种用于形成用于发射短波长的光的Si电致发光（EL）装置的方法。 该方法包括：提供衬底; 形成覆盖所述衬底的第一绝缘体层; 形成覆盖在第一绝缘体层上的富硅氧化物（SRSO）层，其中嵌入尺寸在0.5至5nm范围内的纳米晶体Si; 形成覆盖所述SRSO层的第二绝缘体层; 并形成顶部电极。 通常，SRSO的Si浓度范围为5〜40％。 在一个方面，使用DC溅射工艺形成SRSO层。 另一方面，SRSO形成步骤包括在沉积SRSO之后的快速热退火（RTA）工艺。 同样地，可以在SRSO层沉积之后进行热氧化或等离子体氧化。 响应于上述沉积，退火和氧化过程，Si纳米晶体的尺寸减小。

    Rare earth element-doped silicon/silicon dioxide lattice structure
    44.
    发明申请
    Rare earth element-doped silicon/silicon dioxide lattice structure 失效
    稀土元素掺杂硅/二氧化硅晶格结构

    公开(公告)号：US20060160335A1

    公开(公告)日：2006-07-20

    申请号：US11039463

    申请日：2005-01-19

    申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

    发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

    IPC分类号： H01L21/20

    CPC分类号： C23C14/16 ,  C03C17/34 ,  C23C14/10 ,  C23C28/322 ,  C23C28/323 ,  C23C28/345 ,  C23C28/3455 ,  C23C28/42 ,  H01L21/02164 ,  H01L21/02266 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0259 ,  H01L21/02631 ,  H01L21/02667 ,  H01L21/31608 ,  H01L33/26

    摘要： Provided are an electroluminescence (EL) device and corresponding method for forming a rare earth element-doped silicon (Si)/Si dioxide (SiO2) lattice structure. The method comprises: providing a substrate; DC sputtering a layer of amorphous Si overlying the substrate; DC sputtering a rare earth element; in response, doping the Si layer with the rare earth element; DC sputtering a layer of SiO2 overlying the rare earth-doped Si; forming a lattice structure; annealing; and, in response to the annealing, forming nanocrystals in the rare-earth doped Si having a grain size in the range of 1 to 5 nanometers (nm). In one aspect, the rare earth element and Si are co-DC sputtered. Typically, the steps of DC sputtering Si, DC sputtering the rare earth element, and DC sputtering the SiO2 are repeated 5 to 60 cycles, so that the lattice structure includes the plurality (5-60) of alternating SiO2 and rare earth element-doped Si layers.

    摘要翻译： 提供了一种用于形成稀土元素掺杂硅（Si）/二氧化硅（SiO 2）晶格结构的电致发光（EL）器件和相应的方法。 该方法包括：提供衬底; DC溅射覆盖衬底的非晶硅层; 直流溅射稀土元素; 作为响应，用稀土元素掺杂Si层; DC溅射一层SiO 2，覆盖稀土掺杂的Si; 形成晶格结构; 退火; 并且响应于退火，在具有1至5纳米（nm）范围内的晶粒尺寸的稀土掺杂Si中形成纳米晶体。 一方面，稀土元素和Si共溅射。 通常，DC溅射Si，DC溅射稀土元素和DC溅射SiO 2的步骤重复5至60个循环，使得晶格结构包括多个（5-60）交替的SiO 2和稀土元素掺杂 Si层。

    Selective etching processes of SiO2, Ti and In2O3 thin films for FeRAM device applications
    45.
    发明申请
    Selective etching processes of SiO2, Ti and In2O3 thin films for FeRAM device applications 失效
    用于FeRAM器件应用的SiO2，Ti和In2O3薄膜的选择性蚀刻工艺

    公开(公告)号：US20060091107A1

    公开(公告)日：2006-05-04

    申请号：US10970885

    申请日：2004-10-21

    申请人： Tingkai Li ,  Bruce Ulrich ,  David Evans ,  Sheng Hsu

    发明人： Tingkai Li ,  Bruce Ulrich ,  David Evans ,  Sheng Hsu

    IPC分类号： C03C25/68 ,  H01L21/302 ,  C23F1/00

    CPC分类号： H01L29/6684 ,  C23F4/00 ,  H01L21/28291 ,  H01L21/31116 ,  H01L21/32136

    摘要： A method of selectively etching a three-layer structure consisting of SiO2, In2O3, and titanium, includes etching the SiO2, stopping at the titanium layer, using C3F8 in a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the In2O3 layer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tcp in a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.

    摘要翻译： 选择性地蚀刻由SiO 2，In 2 O 3 N 3和Ti构成的三层结构的方法包括蚀刻SiO 2 ，在钛层上停止，使用C 3 3 F 8 N在约10sccm至30sccm之间的范围内; 在约20sccm至40sccm的范围内的氩气，使用在约1000瓦特至3000瓦特之间的范围内的RF源和在约400瓦特至800瓦特范围内的RF偏压， 约2mtorr至6mtorr; 并且使用在约10sccm至50sccm之间的范围内的BCl蚀刻钛，停止在In 2 N 3 O 3层处; 在约40sccm至80sccm的范围内的氯，在约200瓦特至200瓦特之间的RF偏压下在约200瓦特至500瓦特之间的范围内的T cp < 在约4mtorr至8mtorr的范围内的压力。

    High-density SOI cross-point memory fabricating method
    46.
    发明申请
    High-density SOI cross-point memory fabricating method 有权
    高密度SOI交叉点存储器制造方法

    公开(公告)号：US20060035451A1

    公开(公告)日：2006-02-16

    申请号：US11216680

    申请日：2005-08-31

    申请人： Sheng Hsu

    发明人： Sheng Hsu

    IPC分类号： H01L21/4763

    CPC分类号： G11C13/003 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/78 ,  H01L27/101 ,  H01L27/1203 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/147 ,  H01L45/1683

    摘要： A method for fabricating a high-density silicon-on-insulator (SOI) cross-point memory array and an array structure are provided. The method comprises: selectively forming a hard mask on an SOI substrate, defining memory areas, active device areas, and top electrode areas; etching to remove the exposed silicon (Si) surfaces; selectively forming metal sidewalls adjacent the hard mask; filling the memory areas with memory resistor material; removing the hard mask, exposing the underlying Si active device areas; forming an overlying layer of oxide; etching the oxide to form contact holes to the active device areas; forming diodes in the contact holes; and, forming bottom electrode lines overlying the diodes.

    摘要翻译： 提供了一种用于制造高密度绝缘体上硅（SOI）交叉点存储器阵列和阵列结构的方法。 该方法包括：在SOI衬底上选择性地形成硬掩模，限定存储区域，有源器件区域和顶部电极区域; 蚀刻以去除暴露的硅（Si）表面; 选择性地形成邻近硬掩模的金属侧壁; 用存储电阻材料填充存储区; 去除硬掩模，暴露下面的Si有源器件区域; 形成覆盖层的氧化物; 蚀刻氧化物以形成与有源器件区域的接触孔; 在接触孔中形成二极管; 并且形成覆盖二极管的底部电极线。

    "> Method to form local
    50.
    发明申请
    Method to form local "silicon-on-nothing" or "silicon-on-insulator" wafers with tensile-strained silicon 有权
    用拉伸应变硅形成局部“无硅无硅”或“绝缘体上硅”晶片的方法

    公开(公告)号：US20050214997A1

    公开(公告)日：2005-09-29

    申请号：US10807931

    申请日：2004-03-23

    申请人： Douglas Tweet ,  Sheng Hsu ,  Jer-Shen Maa

    发明人： Douglas Tweet ,  Sheng Hsu ,  Jer-Shen Maa

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/78

    摘要： A method of forming a substrate for use in IC device fabrication includes preparing a silicon substrate, including doping a bulk silicon (100) substrate with ions taken from the group of ions to form a doped substrate taken from the group of doped substrates consisting of n-type doped substrates and p-type doped substrates; forming a first relaxed SiGe layer on the silicon substrate; forming a first tensile-strained silicon cap on the first relaxed SiGe layer; forming a second relaxed SiGe layer on the first tensile-strained silicon cap; forming a second tensile-strained silicon cap on the second relaxed SiGe layer; and completing an IC device.

    摘要翻译： 一种形成用于IC器件制造的衬底的方法包括制备硅衬底，其包括用从离子组中取出的离子掺杂体硅（100）衬底，以形成从由n组成的掺杂衬底组中取出的掺杂衬底 型掺杂衬底和p型掺杂衬底; 在硅衬底上形成第一弛豫的SiGe层; 在第一松弛SiGe层上形成第一拉伸应变硅帽; 在第一拉伸应变硅帽上形成第二松弛SiGe层; 在第二松弛SiGe层上形成第二拉伸应变硅帽; 并完成IC设备。