公开(公告)号：US6166407A

公开(公告)日：2000-12-26

申请号：US138848

申请日：1998-08-24

申请人： Yoshiji Ohta

发明人： Yoshiji Ohta

IPC分类号： G11C14/00 ,  G11C16/02 ,  G11C16/04 ,  H01L27/108

CPC分类号： G11C14/00

摘要： A non-volatile semiconductor memory device includes: a memory cell section having a plurality of memory cells, each of the memory cells including a flash cell section and a DRAM capacitor section, the flash cell section having at least a drain, a source and a floating gate, the drain being connected to a bit line, the DRAM capacitor section having a capacitive element with two electrodes, one of the electrodes being connected to the source, and the other one of the electrodes being connected to a power supply terminal, and the memory cell being constructed in such a manner that electrons are injected into and extracted from the floating gate at least through the drain by a tunnel current; a register section connected to the memory cell section through the bit line; a bit line selector into which a signal from the bit line is input; and a sensing amplifier for receiving an output from the bit line selector as an input signal. According to the present invention, in the normal operation mode, it is possible to achieve a high-speed random access similar to the one in a general DRAM by reading out or rewriting the volatile data stored in the capacitive element section. On the other hand, in the data retaining mode, final information or invariable information can be stored in the non-volatile memory cell section as non-volatile data.

摘要翻译： 非易失性半导体存储器件包括：具有多个存储单元的存储单元部分，每个存储器单元包括闪存单元部分和DRAM电容器部分，闪存单元部分至少具有漏极，源极和 浮动栅极，漏极连接到位线，DRAM电容器部分具有电容元件，具有两个电极，一个电极连接到源极，另一个电极连接到电源端子，以及 存储单元被构造成使得电子至少通过漏极通过隧道电流注入到浮置栅极中并从其中提取; 寄存器部分，通过位线连接到存储器单元部分; 输入来自位线的信号的位线选择器; 以及用于接收来自位线选择器的输出作为输入信号的感测放大器。 根据本发明，在正常操作模式中，通过读出或重写存储在电容元件部分中的易失性数据，可以实现与通常DRAM中的类似的高速随机存取。 另一方面，在数据保留模式中，最终信息或不变信息可以作为非易失性数据存储在非易失性存储单元部分中。

公开(公告)号：US6088265A

公开(公告)日：2000-07-11

申请号：US151087

申请日：1998-09-10

申请人： Yoshiji Ohta

发明人： Yoshiji Ohta

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C17/12 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115

CPC分类号： G11C16/0491 ,  G11C17/126

摘要： In a virtual ground type semiconductor storage device, all of memory cells connected to one word line in blocks of eight memory cells are read in four sense operations. In each read operation, three consecutive main bit lines are discharged by a discharge signal and two memory cells which are each connected to both a discharged main bit line and a charged main bit line are used as read memory cells, whereby the influence of a leak current from both adjacent memory cells upon the read memory cells is suppressed to the minimum. Among adjust cells activated by an adjust signal, ones connected to only the charged main bit lines are designed as programmed cells to reduce a variation in leak current to a sense main bit line due to data retained in the memory cells connected to only the charged main bit lines.

摘要翻译： 在虚拟地面型半导体存储装置中，以四个感测操作读取在八个存储单元的块中连接到一个字线的所有存储单元。 在每次读取操作中，通过放电信号放电三个连续的主位线，并且将两个连接到放电主位线和充电主位线的两个存储器单元用作读存储器单元，由此泄漏的影响 读取存储单元上的两个相邻存储单元的电流被抑制到最小。 在通过调整信号激活的调节单元中，仅连接到带电主位线的调节单元被设计为编程单元，以减少由于仅连接到带电主体的存储器单元中保留的数据而导致感测主位线的泄漏电流的变化 位线。

公开(公告)号：US5995412A

公开(公告)日：1999-11-30

申请号：US167192

申请日：1998-10-06

申请人： Yoshiji Ohta

发明人： Yoshiji Ohta

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C11/5642 ,  G11C2211/5624 ,  G11C2211/5631 ,  G11C2211/5642

摘要： A nonvolatile semiconductor storage device and writing method thereof are capable of concurrently executing a write operation and a verify operation of multi-value data into a plurality of memory cells and writing multi-value data at high speed. Latch circuits of Latch0 and Latch1 store an input multi-value data to be written into a memory cell selected by a bit line and a word line. Multi-value sense amplifiers read the multi-value data written in the memory cell. Based on the input multi-value data (latch nodes Q0#, Q1#) stored in the latch circuits of Latch0 and Latch1 and the multi-value data (sense nodes S0#, S1#) read from the memory cell by the multi-value sense amplifiers, a bit line voltage generating circuit applies a specified voltage for writing the input multi-value data into the memory cell to the bit line connected to the memory cell.

摘要翻译： 非易失性半导体存储装置及其写入方法能够将多值数据的写入操作和验证操作同时执行到多个存储单元中，并以高速写入多值数据。 Latch0和Latch1的锁存电路存储要写入由位线和字线选择的存储单元的输入多值数据。 多值读出放大器读取写入存储单元的多值数据。 基于存储在Latch0和Latch1的锁存电路中的输入多值数据（锁存节点Q0＃，Q1＃）和通过多存储器从存储器单元读取的多值数据（感测节点S0＃，S1＃）， 值读出放大器，位线电压产生电路将用于将输入的多值数据写入存储单元的指定电压施加到连接到存储单元的位线。

公开(公告)号：US5815444A

公开(公告)日：1998-09-29

申请号：US995272

申请日：1997-12-19

申请人： Yoshiji Ohta

发明人： Yoshiji Ohta

IPC分类号： G11C16/02 ,  G11C7/10 ,  G11C16/04 ,  G11C7/00 ,  G11C8/00 ,  G11C11/34

CPC分类号： G11C7/1036 ,  G11C16/0491

摘要： There is provided a serial access system semiconductor storage device capable of reducing access time and decreasing consumption current. A memory cell array including a plurality of memory cells and shift registers and having a plurality of latch circuits connected in series are provided. The shift registers once hold data, received from the memory cell array 1 via a bit line in a read operation, in the latch circuits and serially output the held data in the order in which the latch circuits are arranged. The latch circuits sense-amplify the data stored in the memory cells inside the memory cell array.

摘要翻译： 提供了能够减少访问时间并减少消耗电流的串行存取系统半导体存储装置。 提供包括多个存储单元和移位寄存器并且具有串联连接的多个锁存电路的存储单元阵列。 移位寄存器一旦在锁存电路中保持通过读操作中的位线从存储单元阵列1接收到的数据，并按照锁存电路布置的顺序串行输出保持的数据。 锁存电路对存储在存储单元阵列内的存储单元中的数据进行读出放大。

公开(公告)号：US5475643A

公开(公告)日：1995-12-12

申请号：US150243

申请日：1993-11-09

申请人： Yoshiji Ohta

发明人： Yoshiji Ohta

IPC分类号： G11C11/41 ,  G11C5/06 ,  G11C7/18 ,  G11C11/401 ,  H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/10 ,  H01L27/108 ,  G11C7/02

CPC分类号： G11C5/063 ,  G11C7/18

摘要： An improved signal line system for lines such as bit lines for a semiconductor memory is disclosed. In the signal line system, a first pair of signal lines cross each other at at least one point. At least one portion of one of the signal lines of a second pair is disposed between the signal lines of the first pair. At least one portion of one of the signal lines of a third pair is disposed between one of the signal lines of the first pair and the one signal line of the second pair. At least one portion of one of the signal lines of a fourth pair is disposed to a side of the other one of the signal lines of the first pair. At least one portion of one of the signal lines of a fifth pair is disposed to a side of one of the signal lines of the first pair. The level of the crosstalk between the signal lines can be effectively reduced.

摘要翻译： 公开了用于诸如半导体存储器的位线的线路的改进的信号线系统。 在信号线系统中，第一对信号线至少在一个点处彼此交叉。 第二对的信号线之一的至少一部分设置在第一对的信号线之间。 第三对的信号线之一的至少一部分设置在第一对的信号线和第二对的信号线之间。 第四对的信号线之一的至少一部分设置在第一对信号线的另一条信号线的一侧。 第五对的信号线之一的至少一部分设置在第一对信号线之一的一侧。 可以有效地降低信号线之间的串扰水平。

公开(公告)号：US5134317A

公开(公告)日：1992-07-28

申请号：US705618

申请日：1991-05-29

申请人： Yoshiji Ohta

发明人： Yoshiji Ohta

IPC分类号： G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4094 ,  H01L21/822 ,  H01L27/04

CPC分类号： G11C11/4085 ,  G11C11/4094

摘要： The secondary side of a control capacitor is charged, prior to the precharge period, almost to the source voltage level by a dummy cycle performed after power-on. Then, during the precharge period, a control circuit charges the control capacitor to increase the potential of its primary side to a level higher than the source voltage level V.sub.cc. The potential of the gate of the first transistor is increased to a level higher than the source voltage level, which causes the first transistor to turn on to charge a booster capacitor. At this time, since the secondary side of the booster capacitor is grounded through a third transistor, the primary side of the booster capacitor is held at the source voltage level. When the active period is entered, the third transistor is turned off, and a second transistor which is connected between the power source and the booster capacitor is turned on. This causes the potential of the secondary side of the booster capacitor to rise to the source voltage level. The control circuit operates to ground the control terminal of the first transistor so that the first transistor is turned off, thereby increasing the potential of the primary side of the booster capacitor to a level higher than the source voltage level. The signal of the level higher than the source voltage level is output from the output terminal through a fourth transistor.

摘要翻译： 控制电容器的次级侧在预充电周期之前通过在通电之后执行的虚拟周期几乎达到源极电压电平。 然后，在预充电期间，控制电路对控制电容器充电，将其初级侧的电位增加到高于源电压电平Vcc的电平。 第一晶体管的栅极的电位增加到高于源极电压电平的电平，这使得第一晶体管导通以对升压电容器充电。 此时，由于升压电容器的次级侧通过第三晶体管接地，所以升压电容器的初级侧保持在源电压电平。 当进入有效期间时，第三晶体管截止，连接在电源和升压电容器之间的第二晶体管导通。 这使得升压电容器的次级侧的电位上升到源极电压电平。 控制电路用于将第一晶体管的控制端接地，使得第一晶体管截止，从而将升压电容器的初级侧的电位增加到高于源极电压电平的电平。 高于源极电压电平的电平信号通过第四晶体管从输出端子输出。

公开(公告)号：US09261259B2

公开(公告)日：2016-02-16

申请号：US14127127

申请日：2012-05-25

申请人： Takeshi Shiomi ,  Masaru Nomura ,  Yoshiji Ohta ,  Hiroshi Iwata ,  Koji Takahashi ,  Katsuhiko Kishimoto

发明人： Takeshi Shiomi ,  Masaru Nomura ,  Yoshiji Ohta ,  Hiroshi Iwata ,  Koji Takahashi ,  Katsuhiko Kishimoto

IPC分类号： B60Q1/00 ,  F21V9/08 ,  F21S8/10 ,  F21V7/22 ,  F21V9/16 ,  F21Y101/02

CPC分类号： F21V9/08 ,  B60Q1/0023 ,  F21S41/14 ,  F21S41/141 ,  F21S41/16 ,  F21S41/285 ,  F21V7/22 ,  F21V9/30 ,  F21Y2115/10 ,  F21Y2115/30

摘要： A headlamp (1) that utilizes a laser beam includes a scattered-light emitting unit (21) that emits scattered light upon receipt of a laser beam deviated from a predetermined path through which the laser beam is to pass or a predetermined irradiation region that is to be irradiated by the laser beam.

摘要翻译： 使用激光束的前照灯（1）包括散射光发射单元（21），该散射光发射单元（21）在接收到从激光束将要通过的预定路径偏离的激光束时发射散射光，或者预定的照射区域是 被激光束照射。

公开(公告)号：US20140028375A1

公开(公告)日：2014-01-30

申请号：US14110687

申请日：2012-04-05

申请人： Kenji Komiya ,  Shuji Wakaiki ,  Kohtaroh Kataoka ,  Masaru Nomura ,  Yoshiji Ohta ,  Hiroshi Iwata

发明人： Kenji Komiya ,  Shuji Wakaiki ,  Kohtaroh Kataoka ,  Masaru Nomura ,  Yoshiji Ohta ,  Hiroshi Iwata

IPC分类号： H03K17/30

CPC分类号： H03K17/302 ,  H02M1/088 ,  H02M3/158 ,  H03K17/102 ,  H03K17/122 ,  H03K17/145

摘要： A semiconductor device includes a high breakdown voltage, high Gm first transistor and a low breakdown voltage, low Gm second transistor connected in series between first and second nodes, and a low breakdown voltage, high Gm third transistor connected to the second transistor in parallel. When the second transistor is turned on, the first transistor turns on, and furthermore, when the third transistor is turned on, an electrically conducting state is established between the first and second nodes. The second, low breakdown voltage transistor is turned on to turn on the first, high breakdown voltage transistor, and a turn-on time with only limited variation can be achieved.

摘要翻译： 半导体器件包括高击穿电压，高Gm第一晶体管和低击穿电压，串联连接在第一和第二节点之间的低Gm第二晶体管和低击穿电压，并联连接到第二晶体管的高Gm第三晶体管。 当第二晶体管导通时，第一晶体管导通，此外，当第三晶体管导通时，在第一和第二节点之间建立导电状态。 第二个低击穿电压晶体管导通，以接通第一个高耐压晶体管，并且可以实现只有有限变化的导通时间。

公开(公告)号：US20140009952A1

公开(公告)日：2014-01-09

申请号：US14004527

申请日：2012-03-05

申请人： Masaru Nomura ,  Yoshifumi Yaoi ,  Kohichiroh Adachi ,  Kohtaroh Kataoka ,  Takeshi Shiomi ,  Hiroshi Iwata ,  Yoshiji Ohta

发明人： Masaru Nomura ,  Yoshifumi Yaoi ,  Kohichiroh Adachi ,  Kohtaroh Kataoka ,  Takeshi Shiomi ,  Hiroshi Iwata ,  Yoshiji Ohta

IPC分类号： F21S8/10 ,  H01S5/00

CPC分类号： H01S5/00 ,  F21S41/14 ,  F21S41/147 ,  F21S41/16 ,  F21V9/30 ,  F21Y2101/00 ,  F21Y2115/30 ,  H01S5/005 ,  H01S5/0078 ,  H01S5/042 ,  H01S5/06825 ,  H01S5/4018

摘要： A light emitting device which includes at least one of a laser light source (1), wiring (9), a lens for excitation (2), a luminous body (4), a laser cut filter (6), a half parabolic mirror (5P), and a base (5h), in which a part of the wiring (9) is installed at a portion in which a breakage easily occurs due to at least one deformation of the laser light source (1), the lens for excitation (2), the luminous body (4), the laser cut filter (6), the half parabolic mirror (5P), and the base (5h), or a change in an installation position thereof.

摘要翻译： 一种发光器件，其包括激光源（1），布线（9），激发透镜（2），发光体（4），激光截止滤光器（6），半抛物面镜 （5P）和基部（5h），其中一部分布线（9）安装在由于激光光源（1）的至少一个变形容易发生断裂的部分，用于 激光（2），发光体（4），激光切割滤光片（6），半抛物面镜（5P）和基底（5h），或其安装位置的变化。

公开(公告)号：US08139395B2

公开(公告)日：2012-03-20

申请号：US12777353

申请日：2010-05-11

申请人： Hiroshi Kotaki ,  Yoshiji Ohta ,  Syuji Wakaiki

发明人： Hiroshi Kotaki ,  Yoshiji Ohta ,  Syuji Wakaiki

IPC分类号： G11C11/00

CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/79 ,  G11C2213/82

摘要： There is provided a semiconductor memory device capable of suppressing writing disturbances without increasing the cell array area. A semiconductor memory device has a memory cell array where a number of memory cells having a two-terminal type memory element and a transistor for selection connected in series are aligned in a matrix shape, a first voltage applying circuit for applying a writing voltage pulse to a first bit line, and a second voltage applying circuit for applying a pre-charge voltage to a first and second bit line, such that at the time of the writing of a memory cell, the first voltage applying circuit pre-charges the two ends of the memory cell to the same voltage in advance, and after that, the second voltage applying circuit applies a writing voltage pulse via the first bit line directly connected to the transistor for selection.

摘要翻译： 提供了能够抑制写入干扰而不增加单元阵列区域的半导体存储器件。 半导体存储器件具有存储单元阵列，其中具有两端型存储元件的数量的存储单元和串联连接的选择晶体管以矩阵形状排列;第一施加电压电路，用于将写入电压脉冲施加到 第一位线和第二电压施加电路，用于向第一和第二位线施加预充电电压，使得在写入存储单元时，第一电压施加电路对两端进行预充电 ，然后第二电压施加电路经由直接连接到晶体管的第一位线施加写入电压脉冲以进行选择。