公开(公告)号：US08736534B2

公开(公告)日：2014-05-27

申请号：US11922491

申请日：2006-07-11

申请人： Etsuo Yamamoto ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten

发明人： Etsuo Yamamoto ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3688 ,  G09G2310/0245 ,  G09G2330/02 ,  G09G2330/027

摘要： In one embodiment of the present invention, on each source bus line, an electric charge escaping transistor is provided having the same polarity as a pixel transistor and having a gate to which a turn-off voltage signal of the pixel transistor is supplied. When an active matrix liquid crystal display device is powered off, the turn-off voltage signal is made to reach the GND level before a turn-on voltage signal of the pixel transistor reaches the GND level, so that the pixel transistor and the electric charge escaping transistor are made half-open. This lets electric charges accumulated in the pixel escape to a common electrode TCOM.

摘要翻译： 在本发明的一个实施例中，在每个源极总线上，设置电荷逸出晶体管，其具有与像素晶体管相同的极性，并且具有提供像素晶体管的关断电压信号的栅极。 当有源矩阵液晶显示装置断电时，在像素晶体管的导通电压信号达到GND电平之前，使关断电压信号达到GND电平，使得像素晶体管和电荷 逃逸晶体管制成半开放。 这使得在像素中累积的电荷逃逸到公共电极TCOM。

公开(公告)号：US20130300722A1

公开(公告)日：2013-11-14

申请号：US13981219

申请日：2012-01-23

申请人： Seijirou Gyouten ,  Makoto Yokoyama ,  Takahiro Yamaguchi ,  Shige Furuta

发明人： Seijirou Gyouten ,  Makoto Yokoyama ,  Takahiro Yamaguchi ,  Shige Furuta

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3611 ,  G09G3/3685 ,  G09G2310/0297

摘要： This display device has a demultiplexer (501) formed on a liquid crystal panel, the demultiplexer including three switching elements SW1 to SW3 for time-division drive, which are connected to video signal lines SL1 to SL3. Here, the number of switching control signal lines for transmitting switching control signals GS1 to GS6 to be provided to switching elements coupled to the video signal lines is six, which is twice the number of time divisions, and switching control signals (e.g., GS1 and GS4) with the same timing are individually transmitted by two switching control signal lines, so that the number of switching elements to be coupled to the switching control signal lines as loads can be halved, resulting in reduced waveform rounding of the control signals.

摘要翻译： 该显示装置具有形成在液晶面板上的解复用器（501），该解复用器包括与视频信号线SL1〜SL3连接的三个时分驱动用开关元件SW1〜SW3。 这里，用于发送提供给耦合到视频信号线的开关元件的开关控制信号GS1至GS6的开关控制信号线的数量是时间分割数的两倍的开关控制信号线的数量和切换控制信号（例如GS1和 GS4）通过两个开关控制信号线分别发送，从而将作为负载耦合到开关控制信号线的开关元件的数量减半，导致控制信号的减少的波形舍入。

公开(公告)号：US20120200614A1

公开(公告)日：2012-08-09

申请号：US13501368

申请日：2010-06-02

申请人： Etsuo Yamamoto ,  Shige Furuta ,  Yuhichiroh Murakami ,  Seijirou Gyouten

发明人： Etsuo Yamamoto ,  Shige Furuta ,  Yuhichiroh Murakami ,  Seijirou Gyouten

IPC分类号： G09G3/36 ,  G09G5/10

CPC分类号： G09G3/3614 ,  G09G3/3655 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2300/0876 ,  G09G2310/0264 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0219 ,  G09G2320/0233 ,  G09G2340/0407

摘要： In a display device (i) which carries out a display based on a video signal whose resolution has been converted to higher resolution (high-resolution conversion driving) and (ii) which carries out CC driving, when the resolution of the video signal is converted by a factor of 2 (double-size display), assuming that a direction in which the gate lines extend is a row-wise direction, signal potentials having the same polarity and the same gray scale are supplied to pixel electrodes included in respective two pixels that correspond to two adjacent gate lines and that are adjacent to each other in the column-wise direction (scanning direction), and a direction of change in the signal potentials written to the pixel electrodes from the source lines varies every two adjacent rows according to the polarities of the signal potentials.

摘要翻译： 在基于分辨率被转换为更高分辨率（高分辨率转换驱动）的视频信号和执行CC驱动的（ii））执行显示的显示装置（i）中，当视频信号的分辨率为 转换为2倍（双倍尺寸显示），假设栅极线延伸的方向是行方向，具有相同极性和相同灰度的信号电位被提供给包括在相应两个中的像素电极 对应于两个相邻的栅极线并且在列方向（扫描方向）上彼此相邻的像素，并且从源极线写入像素电极的信号电位的变化方向根据 到信号电位的极性。

公开(公告)号：US20120200549A1

公开(公告)日：2012-08-09

申请号：US13395518

申请日：2010-04-23

申请人： Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

发明人： Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3659 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2320/0219 ,  G09G2330/022

摘要： Provided is a display device which can prevent screen noise caused such that a potential of a common electrode is reversed after a memory mode enters from a refresh period to an entire write-in period, and a method for driving the display device. The memory mode includes (i) an entire write-in period in which a potential of the common electrode (COM) is fixed and the display data is written into all the memory circuits (node (PIX)) in each row and (ii) a refresh period in which the display data which has been written during the entire write-in period is refreshed at least once while the common electrode (COM) is driven. In the memory mode, the potential of the common electrode during the entire write-in period being a potential which the common electrode having been driven had at the end of a refresh period preceding the entire write-in period.

摘要翻译： 提供一种显示装置，其可以防止在从刷新周期进入整个写入周期之后引起公共电极的电位反转的屏幕噪声，以及用于驱动显示装置的方法。 存储模式包括：（i）公共电极（COM）的电位固定并将显示数据写入到每行的所有存储电路（节点（PIX））中的整个写入周期，以及（ii） 在驱动公共电极（COM）的过程中至少刷新一次整个写入周期期间已写入的显示数据的刷新周期。 在存储模式中，公共电极在整个写入周期期间的电位是已经被驱动的公共电极在整个写入周期之前的刷新周期结束时的电位。

公开(公告)号：US20120169753A1

公开(公告)日：2012-07-05

申请号：US13496027

申请日：2010-04-23

申请人： Yuhichiroh Murakami ,  Shige Furuta ,  Yasushi Sasaki ,  Seijirou Gyouten ,  Shuji Nishi

发明人： Yuhichiroh Murakami ,  Shige Furuta ,  Yasushi Sasaki ,  Seijirou Gyouten ,  Shuji Nishi

IPC分类号： G09G5/36 ,  G11C7/00 ,  G11C5/06

CPC分类号： G09G3/3659 ,  G09G2300/0417 ,  G09G2300/0823 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2300/088 ,  G09G2330/022 ,  G11C11/405

摘要： A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.

摘要翻译： 提供了一种存储器件，其包括一个存储器电路，即使在转印部件中使用的转印元件中出现泄漏电流，允许进行刷新操作的电路适当地执行电路的原始操作。 存储单元包括开关电路，第一保持部分，转移部分，第二保持部分，第一控制部分和电压源，并且第一控制部分被控制为处于（i） 第一控制部分执行第一操作，其中第一控制部分处于活动状态或非活动状态，以及（ii）第一控制部分执行第二操作的状态。

公开(公告)号：US20120086689A1

公开(公告)日：2012-04-12

申请号：US13377847

申请日：2010-02-28

申请人： Shige Furuta ,  Etsuo Yamamoto ,  Yuhichiroh Murakami ,  Seijirou Gyouten

发明人： Shige Furuta ,  Etsuo Yamamoto ,  Yuhichiroh Murakami ,  Seijirou Gyouten

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3655 ,  G09G3/3614 ,  G09G3/3659 ,  G09G3/3677 ,  G09G2300/0852 ,  G09G2320/0247

摘要： An embodiment of the present invention switches, in a display driving circuit of a liquid crystal display device which carries out CC driving, between a two-line reversal driving mode in which a polarity of a data signal supplied to a source line is reversed every two horizontal scanning periods and a one-line reversal driving mode in which a polarity of a data signal supplied to a source line is reversed every one horizontal scanning period. In at least one example embodiment, a polarity signal reverses its polarity every two horizontal scanning periods in the two-line reversal driving mode, and reverses its polarity every one horizontal scanning period in the one-line reversal driving mode.

摘要翻译： 本发明的一个实施例在执行CC驱动的液晶显示装置的显示驱动电路中，在提供给源极线的数据信号的极性每二次反转的两线反向驱动模式之间切换 水平扫描周期和提供给源极线的数据信号的极性在每一个水平扫描周期反转的单线反转驱动模式。 在至少一个示例性实施例中，极性信号在双线反向驱动模式中每两个水平扫描周期反转其极性，并且在单行反向驱动模式中每一个水平扫描周期反转其极性。

公开(公告)号：US06407796B2

公开(公告)日：2002-06-18

申请号：US09873393

申请日：2001-06-05

申请人： Naoyuki Tajima ,  Yasunori Chikawa ,  Shunichi Murahashi ,  Seijirou Gyouten

发明人： Naoyuki Tajima ,  Yasunori Chikawa ,  Shunichi Murahashi ,  Seijirou Gyouten

IPC分类号： G02F11345

CPC分类号： H01L23/5387 ,  H01L2224/73204 ,  H01L2924/09701 ,  H05K1/14 ,  H05K3/361

摘要： A tape carrier package is provided, which includes: a line provided on one surface of a tape substrate; and a semiconductor chip mounted on an other surface of the tape substrate, the semiconductor chip having an electrode which is electrically connected to the line. The line extends from one end to an opposite end of the tape substrate and includes a connection where an intermediate line portion provided in a middle between the ends is electrically connected to the electrode.

摘要翻译： 提供一种胶带载体包装，其包括：设置在带基材的一个表面上的线; 以及安装在所述带基板的另一表面上的半导体芯片，所述半导体芯片具有电连接到所述线的电极。 该线从带基材的一端延伸到另一端，并且包括其中设置在端部之间的中间的中间线部分与电极电连接的连接。

公开(公告)号：US5786800A

公开(公告)日：1998-07-28

申请号：US630973

申请日：1996-04-12

申请人： Seijirou Gyouten

发明人： Seijirou Gyouten

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3692 ,  G09G3/3622

摘要： The data signals retained in the data latch circuit are captured securely in the line latch circuit. The data latch control circuit sequentially creates data latch control signals DLC having timing values shifted from one another by one period of a data latch clock signal DLCK. The first n-bit display data DA is retained in the D latch circuits at the first stage of the data latch circuit in accordance with the first signal DLC and then retained in the D latch circuits at the second stage in accordance with the second signal DLC. Furthermore, the second display data DA is retained in the D latch circuits of the data latch circuit. The display data DA for one scanning electrode is retained in the line latch circuit by a capture signal LPS delivered between the termination of the delivery of a horizontal synchronizing signal LP and the termination of the delivery of the first signal DLCK to the next scanning electrode.

摘要翻译： 保留在数据锁存电路中的数据信号被牢固地捕获在线路锁存电路中。 数据锁存控制电路依次创建数据锁存控制信号DLC，数据锁存控制信号DLC具有从数据锁存时钟信号DLCK彼此相移一个周期的定时值。 第一n比特显示数据DA根据第一信号DLC保留在数据锁存电路的第一级的D锁存电路中，然后根据第二信号DLC保留在第二级的D锁存电路 。 此外，第二显示数据DA被保留在数据锁存电路的D锁存电路中。 一个扫描电极的显示数据DA通过在水平同步信号LP的传送结束和第一信号DLCK传送到下一个扫描电极的终止之间传递的捕获信号LPS保留在线路锁存电路中。

公开(公告)号：US5726491A

公开(公告)日：1998-03-10

申请号：US672587

申请日：1996-06-28

申请人： Naoyuki Tajima ,  Yoshinori Ogawa ,  Seijirou Gyouten

发明人： Naoyuki Tajima ,  Yoshinori Ogawa ,  Seijirou Gyouten

IPC分类号： H01L21/60 ,  H01L23/28 ,  H01L23/31 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L24/50 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49572 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082

摘要： A tape carrier package of the invention includes: an insulating film having a device hole; a conductor pattern formed on the insulating film; and conductor leads electrically connected to the conductor pattern and projected inward beyond the edge of the device hole, and the conductor leads is electrically connected to electrode pads of a semiconductor chip. In this arrangement, the electrode pads of the semiconductor chip are arranged in at least two rows which are parallel to opposite two sides of the semiconductor chip, the two opposite rows of pads are disposed closer to the center of the two rows than to the edge of semiconductor chip, and the element-forming surface of the entire semiconductor chip containing the region between the insulating film and the semiconductor chip, is sealed with a sealing resin, except the part of the electrode pads.

摘要翻译： 本发明的载带封装包括：具有器件孔的绝缘膜; 形成在绝缘膜上的导体图案; 以及导体引线，其电连接到导体图案并向内突出超出器件孔的边缘，并且导体引线电连接到半导体芯片的电极焊盘。 在这种布置中，半导体芯片的电极焊盘布置成平行于半导体芯片的相对两侧的至少两行，两个相对的焊盘排设置成比两边的中心更靠近边缘 以及包含绝缘膜和半导体芯片之间的区域的整个半导体芯片的元件形成表面除了电极焊盘的一部分之外用密封树脂密封。

公开(公告)号：US09336740B2

公开(公告)日：2016-05-10

申请号：US14127525

申请日：2012-06-26

申请人： Shige Furuta ,  Yuhichiroh Murakami ,  Makoto Yokoyama ,  Seijirou Gyouten

发明人： Shige Furuta ,  Yuhichiroh Murakami ,  Makoto Yokoyama ,  Seijirou Gyouten

IPC分类号： G11C19/28 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： A shift register is disclosed which includes, at respective stages, unit circuits (11) each including (i) a flip-flop (11a) including first and second CMOS circuits and (ii) a signal generation circuit (11b) for generating an output signal (SROUTk) for the current stage with use of an output (Q, QB) of the flip-flop (11a), the shift register including a floating control circuit (11c) between a gate terminal of an output transistor (Tr7) of the signal generation circuit (11b) and a Q terminal. This makes it possible to reduce a circuit scale of a display driving circuit without causing a shift register to malfunction.

摘要翻译： 公开了一种移位寄存器，其在各个阶段包括单元电路（11），每个单元电路（11）包括（i）包括第一和第二CMOS电路的触发器（11a）和（ii）用于产生输出的信号生成电路 信号（SROUTk），其使用触发器（11a）的输出（Q，QB），所述移位寄存器包括在所述触发器（11a）的输出晶体管（Tr7）的栅极端之间的浮动控制电路（11c） 信号发生电路（11b）和Q端子。 这使得可以在不引起移位寄存器故障的情况下减小显示驱动电路的电路规模。