公开(公告)号：US20140157067A1

公开(公告)日：2014-06-05

申请号：US14089730

申请日：2013-11-25

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10

CPC classification number: G11C29/56012 ,  G06F11/1048 ,  G11C29/14 ,  G11C29/56004 ,  G11C2029/5602

Abstract: A device under test has a connection interface, a controller, and a functional block. The connection interface is used to receive a test pattern transmitted at a first clock rate and output a functional test result. The controller is used to sample the test pattern by using a second clock rate and accordingly generate a sampled test pattern, wherein the second clock rate is higher than the first clock rate. The functional block is used to perform a designated function upon the sampled test pattern and accordingly generate the functional test result.

Abstract translation: 被测设备具有连接接口，控制器和功能块。 连接接口用于接收以第一时钟速率发送的测试码，并输出功能测试结果。 控制器用于通过使用第二时钟速率对测试模式进行采样，并因此产生采样的测试模式，其中第二时钟速率高于第一时钟速率。 功能块用于在采样的测试图案上执行指定的功能，从而产生功能测试结果。

公开(公告)号：US20140032993A1

公开(公告)日：2014-01-30

申请号：US13950301

申请日：2013-07-25

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Li-Sheng Kan

IPC: G06F11/10 ,  G06F12/02

CPC classification number: G06F11/1068 ,  G06F3/00 ,  G06F11/14 ,  G06F12/0246 ,  G06F2212/1032

Abstract: A method for managing data stored in a flash memory is provided, where the flash memory includes a plurality of blocks. The method includes: providing a program list, where the program list records information about programmed blocks of the plurality of blocks and sequence of write times of the programmed blocks; detecting quality of a first block of the plurality of blocks to generate a detecting result, where the first block is the programmed block that has an earliest write time; and determining whether to move contents of the first block to a blank block, and to delete the contents of the first block according to the detecting result.

Abstract translation: 提供了一种管理存储在闪存中的数据的方法，其中闪速存储器包括多个块。 该方法包括：提供程序列表，其中程序列表记录关于多个块的编程块的信息和编程块的写入时间序列; 检测多个块的第一块的质量以产生检测结果，其中第一块是具有最早写入时间的编程块; 以及确定是否将第一块的内容移动到空白块，并且根据检测结果来删除第一块的内容。

公开(公告)号：US20130201763A1

公开(公告)日：2013-08-08

申请号：US13802625

申请日：2013-03-13

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/3427 ,  G11C29/52 ,  G11C2211/5644 ,  G11C2211/5648 ,  H03M13/152

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract translation: 用于读取存储在闪速存储器中的数据的方法至少包括以下步骤：控制闪速存储器对包括在闪速存储器中的多个存储器单元执行多个读取操作; 分别从存储单元获取多个位序列，其中读操作通过利用不同的控制栅极电压设置从存储单元读取预定位序的位; 以及根据比特序列的二进制数字分配特性来确定存储器单元的读出信息。

公开(公告)号：US20130107625A1

公开(公告)日：2013-05-02

申请号：US13658086

申请日：2012-10-23

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Ching-Hui Lin ,  Yang-Chih Shen ,  Chun-Chieh Kuo

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641

Abstract: The invention provides a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a flash memory and a flash memory controller. The flash memory comprises a write circuit and a memory cell array comprising a plurality of memory cells, wherein the write circuit is coupled to the memory cell array to write data in the memory cells. The flash memory controller is coupled to the write circuit, obtains a total capacity and a used data amount of the flash memory, and directs the write circuit to perform data writing in a one-bit mode when a ratio of the user data amount to the total capacity is less than a first predetermined value.

Abstract translation: 本发明提供一种闪存装置。 在一个实施例中，闪存装置包括闪速存储器和闪存控制器。 闪速存储器包括写电路和包括多个存储单元的存储单元阵列，其中写电路耦合到存储单元阵列以将数据写入存储单元。 闪速存储器控制器耦合到写入电路，获得闪存的总容量和使用的数据量，并且当用户数据量与存储器的比率相对应时，引导写入电路以一位模式执行数据写入 总容量小于第一预定值。

公开(公告)号：US20250077085A1

公开(公告)日：2025-03-06

申请号：US18810487

申请日：2024-08-20

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F3/06

Abstract: A flash memory controller, to be coupled between a host device and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host device to form a super block stored within the flash memory module, to generate wordline-dimensional parity data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional parity data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional parity data and the finger-dimensional parity data so as to obtain correct data content of the specific data.

公开(公告)号：US20250006252A1

公开(公告)日：2025-01-02

申请号：US18621085

申请日：2024-03-28

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C29/52

Abstract: A data programming method for a flash memory includes: writing a write data to a page buffer of the flash memory; encoding the write data to generate first parity data corresponding to the write data, and writing the first parity data to the page buffer; while generating the first parity data, performing an error detection based on the write data and the first parity data to produce an error detection result; and when the error detection result indicates that there is no error in the first parity data, issuing a program command to the flash memory to program the write data and the first parity data in the page buffer into a flash memory element of the flash memory.

公开(公告)号：US20240386970A1

公开(公告)日：2024-11-21

申请号：US18784972

申请日：2024-07-26

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26 ,  G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C29/52 ,  H03M13/15

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

公开(公告)号：US20240329845A1

公开(公告)日：2024-10-03

申请号：US18129028

申请日：2023-03-30

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679 ,  H03M13/45

Abstract: The present invention provides a control method of the memory device. In the operation of the memory device, the soft information is compressed by a control circuit within the flash memory module, so that the second readout information including the compressed soft information transmitted by the flash memory module has much smaller data size. Therefore, the performance of the memory interface will not be affected due to the bandwidth occupied by the soft information transmission.

公开(公告)号：US20240154624A1

公开(公告)日：2024-05-09

申请号：US18413007

申请日：2024-01-15

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: H03M13/09 ,  G06F11/10 ,  G11C11/56 ,  G11C16/10 ,  H03M13/00 ,  H03M13/15

CPC classification number: H03M13/098 ,  G06F11/1072 ,  G06F11/108 ,  G11C11/5628 ,  G11C16/10 ,  H03M13/1515 ,  H03M13/611 ,  G11C16/26

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

公开(公告)号：US20240028198A1

公开(公告)日：2024-01-25

申请号：US17870861

申请日：2022-07-22

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/0656 ,  G06F3/0679

Abstract: A method for performing data retention management of a memory device with aid of pre-shutdown control and associated apparatus are provided. The method may include: receiving a predetermined host command from a host device; in response to the predetermined host command, performing a re-programming procedure on the NV memory, for enhancing data storage reliability of the memory device, for example, reading stored data from at least one source location within the at least one NV memory element to prepare re-programming data according to the stored data, and programming the re-programming data into at least one destination location within the at least one NV memory element to be replacement of the stored data; and in response to the re-programming procedure being completed, sending completion information of the predetermined host command to the host device, to allow the host device to trigger the shutdown of the memory device.