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    Sense Amplifier Circuit For Reading Data In A Flash Memory Cell
    41.
    发明申请
    Sense Amplifier Circuit For Reading Data In A Flash Memory Cell 审中-公开

    公开(公告)号：US20190066805A1

    公开(公告)日：2019-02-28

    申请号：US15687092

    申请日：2017-08-25

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong

    IPC: G11C16/28 ,  G11C16/34

    Abstract: Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the value stored in the selected memory cell in the data block. The use of one or more localized boost circuits allow the embodiments to utilize lower operating voltages than prior art sense amplifier circuits, resulting in reduced power consumption.

    Flash memory system using complementary voltage supplies
    42.
    发明授权
    Flash memory system using complementary voltage supplies 有权

    公开(公告)号：US10186322B2

    公开(公告)日：2019-01-22

    申请号：US15361473

    申请日：2016-11-27

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC: G11C16/30 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C5/14 ,  G11C8/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521

    Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

    Mixed voltage non-volatile memory integrated circuit with power saving
    50.
    发明授权
    Mixed voltage non-volatile memory integrated circuit with power saving 有权
    混合电压非易失性存储器集成电路，省电

    公开(公告)号：US09378838B2

    公开(公告)日：2016-06-28

    申请号：US14257335

    申请日：2014-04-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC: G11C16/04 ,  G11C16/30 ,  G11C5/14 ,  G11C16/08 ,  G11C11/56

    CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/08

    Abstract: An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage and is generated by a voltage regulator that receives the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. The voltage regulator is enabled by a controller.

    Abstract translation: 集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。 第二电压小于第一电压，并由接收第一电压的电压调节器产生。 可在第一电压下操作的第一电路在集成电路管芯中。 可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。 电压调节器由控制器使能。

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