公开(公告)号：US07167400B2

公开(公告)日：2007-01-23

申请号：US10873968

申请日：2004-06-22

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C8/08

摘要： An apparatus and method for generating a control pulse for closing an active wordline in a memory device is provided. A timeout generator circuit having a time delay portion and a reset portion may be used to generate a close signal. The time delay portion may define a predetermined time delay interval. The timeout generator may be used in combination with an address transition detector in a refresh controller for a memory device. A method is given in which a control pulse is generated in response to an active mode signal, a timer measuring a predetermined time delay interval is activated in response to the control pulse, a close signal is produced in response to the expiration of the predetermined time delay interval, and the active wordline is closed in response to the close signal.

摘要翻译： 提供一种用于产生用于关闭存储器件中的有效字线的控制脉冲的装置和方法。 具有时间延迟部分和复位部分的超时发生器电路可用于产生闭合信号。 时间延迟部分可以定义预定的时间延迟间隔。 超时发生器可以与用于存储器设备的刷新控制器中的地址转换检测器组合使用。 给出了响应于有源模式信号产生控制脉冲的方法，响应于控制脉冲激活测量预定时间延迟间隔的定时器，响应于预定时间的期满而产生闭合信号 延迟间隔，并且有效字线响应于关闭信号而闭合。

公开(公告)号：US07106637B2

公开(公告)日：2006-09-12

申请号：US10754658

申请日：2004-01-08

申请人： Simon J. Lovett ,  Cliff Zitlaw ,  Brian M. Shirley ,  Roger D. Norwood ,  John F. Schreck

发明人： Simon J. Lovett ,  Cliff Zitlaw ,  Brian M. Shirley ,  Roger D. Norwood ,  John F. Schreck

IPC分类号： G11C7/00

CPC分类号： G11C8/18 ,  G11C7/22

摘要： An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

公开(公告)号：US07034507B2

公开(公告)日：2006-04-25

申请号：US10613236

申请日：2003-07-03

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： H01M10/44 ,  H01M10/46

CPC分类号： H02J7/007 ,  G01K1/02 ,  G01K1/20 ,  G01K13/00 ,  H02J7/0052

摘要： A temperature sensing device can be embedded in a memory circuit in order to sense the temperature of the memory circuit. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature.

摘要翻译： 温度感测装置可嵌入存储器电路中以便感测存储器电路的温度。 当振荡器的温度降低时，一个振荡器产生温度可变信号，随着振荡器的温度升高而频率增加，并降低频率。 温度不变振荡器产生由振荡器读取逻辑控制并指示温度感测周期的固定宽度信号。 n位计数器由温度可变信号计时，而固定宽度信号启用/禁止计数器。 计数器计数越快，固定宽度信号指示的感测周期结束时的计数值越大。 较大的计数值表示较暖的温度。 较小的计数值表示较冷的温度。

公开(公告)号：US06750497B2

公开(公告)日：2004-06-15

申请号：US10225423

申请日：2002-08-22

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： H01L27108

CPC分类号： G11C11/404 ,  G11C11/405 ,  G11C11/406 ,  G11C11/40603 ,  G11C2211/4065

摘要： A high-speed transparent refresh DRAM-based memory cell and architecture are disclosed. Each memory cell consists of 4 transistors configured to incorporate differential data storage (i.e., storing a true logic state and a complementary logic state), with each pair of transistors having a dual port configuration and forming one of a complementary pair of storage nodes for the memory cell. Each memory cell is coupled to 2 wordlines and 4 digit lines. Since the memory cell stores complementary data, and since a logic LOW state is rewritten to a given memory cell faster than a logic HIGH state is rewritten, the logic LOW state is rewritten and the complementary logic state is known to be a logic HIGH state. As a result, both the logic LOW and logic HIGH states are rewritten to the memory cell faster than independently writing a logic HIGH state.

公开(公告)号：US06292403B1

公开(公告)日：2001-09-18

申请号：US09521190

申请日：2000-03-07

申请人： Ashish Pancholy ,  Cathal G. Phelan ,  Simon J. Lovett

发明人： Ashish Pancholy ,  Cathal G. Phelan ,  Simon J. Lovett

IPC分类号： G11C700

CPC分类号： G11C7/1039 ,  G11C8/18 ,  G11C11/4087

摘要： A circuit including an address bus providing random addresses for a random access memory array, and a register configured to receive, store or transfer (i) a first random address from the address bus in response to a first periodic signal transition and (ii) a second random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle, and are preferably complementary to each other. In a further embodiment, the invention concerns a random access memory having an address bus providing random address information for a random access memory array, a predecoder configured to at least partially decode the random address information from the address bus, a register configured to receive, store or transfer (i) a first at least partially decoded random address from the address bus in response to a first periodic signal transition and (ii) a second at least partially decoded random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle; and a postdecoder configured to activate the random addresses in the random access memory in response to receiving the random addresses from the register.

摘要翻译： 一种包括为随机存取存储器阵列提供随机地址的地址总线的电路，以及响应于第一周期性信号转换而从地址总线接收，存储或传输（i）第一随机地址的寄存器，以及（ii） 响应于第二周期性信号转换，来自地址总线的第二随机地址，其中第一和第二周期信号转换发生在单个周期信号周期内，并且优选地彼此互补。 在另一实施例中，本发明涉及一种随机存取存储器，其具有为随机存取存储器阵列提供随机地址信息的地址总线，被配置为至少部分地从地址总线解码随机地址信息的预解码器，配置成接收， 响应于第一周期性信号转换，存储或传输（i）来自地址总线的第一至少部分解码的随机地址和（ii）响应于第二周期性信号转换的来自地址总线的第二至少部分解码的随机地址 ，其中所述第一和第二周期信号转换发生在单周期信号周期内; 以及后置解码器，被配置为响应于从寄存器接收到随机地址来激活随机存取存储器中的随机地址。

公开(公告)号：US5889416A

公开(公告)日：1999-03-30

申请号：US958500

申请日：1997-10-27

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： H03K19/0948 ,  H03K19/20 ,  H03K19/094

CPC分类号： H03K19/0948

摘要： A NAND gate including a pull-down circuit coupled to a pull-up circuit. The NAND gate is configured to drive an output signal to a high logic state at a substantially uniform slew rate regardless of the number of input signals that are in a low logic state. The pull-up circuit may include a plurality of load circuits each coupled to a corresponding one of the plurality of input signals, and a plurality of transistor circuits each comprising a plurality of transistors coupled in parallel with each other and coupled to a corresponding one of the plurality of input signals or a complement of a corresponding one of the plurality of input signals. The plurality of load circuits and the plurality of transistors may each include a p-channel MOS (PMOS) transistor. The NAND gate may be incorporated into a decoder of a synchronous or asynchronous input path circuit to generally reduce the setup and hold time window of the input path circuit.

摘要翻译： 包括耦合到上拉电路的下拉电路的NAND门。 NAND门被配置为以基本均匀的转换速率将输出信号驱动到高逻辑状态，而与处于低逻辑状态的输入信号的数量无关。 上拉电路可以包括多个负载电路，每个负载电路分别耦合到多个输入信号中的一个输入信号，以及多个晶体管电路，每个晶体管电路包括彼此并联耦合的多个晶体管，并耦合到 所述多个输入信号或所述多个输入信号中的相应一个输入信号的互补。 多个负载电路和多个晶体管可以各自包括p沟道MOS（PMOS）晶体管。 NAND门可以并入到同步或异步输入路径电路的解码器中，以大体上减少输入路径电路的建立和保持时间窗口。

公开(公告)号：US09772969B2

公开(公告)日：2017-09-26

申请号：US13308333

申请日：2011-11-30

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： G06F13/42 ,  G06F13/16 ,  G11C11/413 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4076

CPC分类号： G06F13/4234 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4243 ,  G11C7/1045 ,  G11C7/1072 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/413

摘要： A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

公开(公告)号：US08082413B2

公开(公告)日：2011-12-20

申请号：US12634580

申请日：2009-12-09

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： G06F12/00

CPC分类号： G06F13/4234 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4243 ,  G11C7/1045 ,  G11C7/1072 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/413

摘要： A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device. The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

摘要翻译： 一种用于检测和启动存储器设备的存储器访问模式的存储器访问模式检测电路和方法。 存储器访问模式检测电路接收存储器地址信号，控制信号和时钟信号，并且响应于存储器地址信号的接收或控制信号的第一组合而产生第一模式检测信号。 在检测信号之后产生第一模式启动信号，以启动第一模式存储器访问操作。 响应于接收到控制信号和活动时钟信号的第二组合，存储器访问模式检测电路还产生第二模式检测信号以启动第二模式存储器访问操作并且抑制第一模式检测信号的产生，从而 取消第一模式存储器存取操作。

公开(公告)号：US20100277998A1

公开(公告)日：2010-11-04

申请号：US12772681

申请日：2010-05-03

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： G11C7/06

CPC分类号： G11C11/4091 ,  G11C7/065

摘要： Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated.

摘要翻译： 提供了系统，装置，存储器件，读出放大器和方法，诸如包括输入节点的系统，具有耦合到输入节点的栅极的第一晶体管和耦合到输入节点的另一个栅极的第二晶体管 。 在一个或多个实施例中，第二晶体管具有比第一晶体管更大的激活电压阈值，并且第一晶体管放大存在于输入节点上的信号。 在一个这样的实施例中，在第一晶体管放大信号之后，第二晶体管在第一晶体管被去激活时保持输入节点上的放大信号。

公开(公告)号：US07660172B2

公开(公告)日：2010-02-09

申请号：US12077577

申请日：2008-03-20

申请人： Simon J. Lovett ,  Dean Gans

发明人： Simon J. Lovett ,  Dean Gans

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104 ,  G11C2207/2254

摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 根据一个实施例，组合由多个感测放大器组成，每个具有用于接收时钟信号的输入。 数据总线用于响应于输入到多个感测放大器的时钟信号而从多个感测放大器接收数据。 跟踪电路响应于时钟信号以产生控制信号。 多个锁存器响应于用于锁存来自总线的数据的控制信号。 控制信号具有等于最后数据位到达多个锁存器所需的时间的延迟。 该延迟可以等于将时钟信号输入到多个感测放大器中的最后一个，延迟最后一个感测放大器加上数据总线延迟的延迟。 可以通过多种方式实现延迟量，这些方式将电延迟与与跟踪电路的位置固有相关的延迟组合。 例如，控制信号的延迟可以通过将跟踪电路定位为接近多个感测放大器中的最后一个感测放大器并且为跟踪电路提供等于多个感测中的最后一个的延迟的电延迟来实现 放大器 由于管理摘要的规则，本摘要不应用于解释索赔。