摘要:
A non-volatile semiconductor memory device includes: a memory cell section having a plurality of memory cells, each of the memory cells including a flash cell section and a DRAM capacitor section, the flash cell section having at least a drain, a source and a floating gate, the drain being connected to a bit line, the DRAM capacitor section having a capacitive element with two electrodes, one of the electrodes being connected to the source, and the other one of the electrodes being connected to a power supply terminal, and the memory cell being constructed in such a manner that electrons are injected into and extracted from the floating gate at least through the drain by a tunnel current; a register section connected to the memory cell section through the bit line; a bit line selector into which a signal from the bit line is input; and a sensing amplifier for receiving an output from the bit line selector as an input signal. According to the present invention, in the normal operation mode, it is possible to achieve a high-speed random access similar to the one in a general DRAM by reading out or rewriting the volatile data stored in the capacitive element section. On the other hand, in the data retaining mode, final information or invariable information can be stored in the non-volatile memory cell section as non-volatile data.
摘要:
In a virtual ground type semiconductor storage device, all of memory cells connected to one word line in blocks of eight memory cells are read in four sense operations. In each read operation, three consecutive main bit lines are discharged by a discharge signal and two memory cells which are each connected to both a discharged main bit line and a charged main bit line are used as read memory cells, whereby the influence of a leak current from both adjacent memory cells upon the read memory cells is suppressed to the minimum. Among adjust cells activated by an adjust signal, ones connected to only the charged main bit lines are designed as programmed cells to reduce a variation in leak current to a sense main bit line due to data retained in the memory cells connected to only the charged main bit lines.
摘要:
A nonvolatile semiconductor storage device and writing method thereof are capable of concurrently executing a write operation and a verify operation of multi-value data into a plurality of memory cells and writing multi-value data at high speed. Latch circuits of Latch0 and Latch1 store an input multi-value data to be written into a memory cell selected by a bit line and a word line. Multi-value sense amplifiers read the multi-value data written in the memory cell. Based on the input multi-value data (latch nodes Q0#, Q1#) stored in the latch circuits of Latch0 and Latch1 and the multi-value data (sense nodes S0#, S1#) read from the memory cell by the multi-value sense amplifiers, a bit line voltage generating circuit applies a specified voltage for writing the input multi-value data into the memory cell to the bit line connected to the memory cell.
摘要:
There is provided a serial access system semiconductor storage device capable of reducing access time and decreasing consumption current. A memory cell array including a plurality of memory cells and shift registers and having a plurality of latch circuits connected in series are provided. The shift registers once hold data, received from the memory cell array 1 via a bit line in a read operation, in the latch circuits and serially output the held data in the order in which the latch circuits are arranged. The latch circuits sense-amplify the data stored in the memory cells inside the memory cell array.
摘要:
An improved signal line system for lines such as bit lines for a semiconductor memory is disclosed. In the signal line system, a first pair of signal lines cross each other at at least one point. At least one portion of one of the signal lines of a second pair is disposed between the signal lines of the first pair. At least one portion of one of the signal lines of a third pair is disposed between one of the signal lines of the first pair and the one signal line of the second pair. At least one portion of one of the signal lines of a fourth pair is disposed to a side of the other one of the signal lines of the first pair. At least one portion of one of the signal lines of a fifth pair is disposed to a side of one of the signal lines of the first pair. The level of the crosstalk between the signal lines can be effectively reduced.
摘要:
The secondary side of a control capacitor is charged, prior to the precharge period, almost to the source voltage level by a dummy cycle performed after power-on. Then, during the precharge period, a control circuit charges the control capacitor to increase the potential of its primary side to a level higher than the source voltage level V.sub.cc. The potential of the gate of the first transistor is increased to a level higher than the source voltage level, which causes the first transistor to turn on to charge a booster capacitor. At this time, since the secondary side of the booster capacitor is grounded through a third transistor, the primary side of the booster capacitor is held at the source voltage level. When the active period is entered, the third transistor is turned off, and a second transistor which is connected between the power source and the booster capacitor is turned on. This causes the potential of the secondary side of the booster capacitor to rise to the source voltage level. The control circuit operates to ground the control terminal of the first transistor so that the first transistor is turned off, thereby increasing the potential of the primary side of the booster capacitor to a level higher than the source voltage level. The signal of the level higher than the source voltage level is output from the output terminal through a fourth transistor.
摘要:
A headlamp (1) that utilizes a laser beam includes a scattered-light emitting unit (21) that emits scattered light upon receipt of a laser beam deviated from a predetermined path through which the laser beam is to pass or a predetermined irradiation region that is to be irradiated by the laser beam.
摘要:
A semiconductor device includes a high breakdown voltage, high Gm first transistor and a low breakdown voltage, low Gm second transistor connected in series between first and second nodes, and a low breakdown voltage, high Gm third transistor connected to the second transistor in parallel. When the second transistor is turned on, the first transistor turns on, and furthermore, when the third transistor is turned on, an electrically conducting state is established between the first and second nodes. The second, low breakdown voltage transistor is turned on to turn on the first, high breakdown voltage transistor, and a turn-on time with only limited variation can be achieved.
摘要:
A light emitting device which includes at least one of a laser light source (1), wiring (9), a lens for excitation (2), a luminous body (4), a laser cut filter (6), a half parabolic mirror (5P), and a base (5h), in which a part of the wiring (9) is installed at a portion in which a breakage easily occurs due to at least one deformation of the laser light source (1), the lens for excitation (2), the luminous body (4), the laser cut filter (6), the half parabolic mirror (5P), and the base (5h), or a change in an installation position thereof.
摘要:
There is provided a semiconductor memory device capable of suppressing writing disturbances without increasing the cell array area. A semiconductor memory device has a memory cell array where a number of memory cells having a two-terminal type memory element and a transistor for selection connected in series are aligned in a matrix shape, a first voltage applying circuit for applying a writing voltage pulse to a first bit line, and a second voltage applying circuit for applying a pre-charge voltage to a first and second bit line, such that at the time of the writing of a memory cell, the first voltage applying circuit pre-charges the two ends of the memory cell to the same voltage in advance, and after that, the second voltage applying circuit applies a writing voltage pulse via the first bit line directly connected to the transistor for selection.