公开(公告)号：US11916567B2

公开(公告)日：2024-02-27

申请号：US17570658

申请日：2022-01-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya Krishnaswamy Nurani ,  Joseph Palackal Mathew ,  Prasanth K ,  Visvesvaraya Appala Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  G11C27/02

CPC classification number: H03M1/1245 ,  G11C27/02 ,  H03M1/121

Abstract: An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. A first capacitor is coupled between the first and second transistors and a second capacitor is coupled between the third and fourth transistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.

公开(公告)号：US11888459B2

公开(公告)日：2024-01-30

申请号：US17463886

申请日：2021-09-01

Applicant: Texas Instruments Incorporated

Inventor： Shagun Dusad ,  Vysakh Karthikeyan ,  Naveen Mahadev ,  Rafi Mahammad

IPC: H03H7/42 ,  H03H7/00 ,  H01F27/28 ,  H03H7/38

CPC classification number: H03H7/42 ,  H01F27/28 ,  H03H7/004 ,  H03H7/38

Abstract: A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.

公开(公告)号：US20220247420A1

公开(公告)日：2022-08-04

申请号：US17467561

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Eeshan Miglani ,  Chirag Chandrahas Shetty ,  Neeraj Shrivastava ,  Shagun Dusad ,  Srinivas Kumar Reddy Naru ,  Nithin Gopinath ,  Charls Babu ,  Shivam Srivastava ,  Viswanathan Nagarajan ,  Jagannathan Venkataraman ,  Harshit Moondra ,  Prasanth K ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

公开(公告)号：US20220173711A1

公开(公告)日：2022-06-02

申请号：US17463886

申请日：2021-09-01

Applicant: Texas Instruments Incorporated

Inventor： Shagun Dusad ,  Vysakh Karthikeyan ,  Naveen Mahadev ,  Rafi Mahammad

IPC: H03H7/42

Abstract: A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.

公开(公告)号：US11309902B2

公开(公告)日：2022-04-19

申请号：US16714835

申请日：2019-12-16

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Narasimhan Rajagopal ,  Shagun Dusad ,  Viswanathan Nagarajan ,  Visvesvaraya Appala Pentakota

IPC: H03M1/06 ,  H03M1/04 ,  H03M1/16

Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

公开(公告)号：US11277145B2

公开(公告)日：2022-03-15

申请号：US16850597

申请日：2020-04-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya Krishnaswamy Nurani ,  Joseph Palackal Mathew ,  Prasanth K ,  Visvesvaraya Appala Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  G11C27/02

Abstract: A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.

公开(公告)号：US10892835B2

公开(公告)日：2021-01-12

申请号：US16058007

申请日：2018-08-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun Dusad ,  Nagarajan Viswanathan

IPC: H04B17/309 ,  H04L1/24 ,  H04L25/02 ,  H04B17/336 ,  H04L1/20

Abstract: A system includes a pseudorandom binary sequence (PRBS) generator configured to generate a first PRBS and a second PRBS and an exclusive-OR logic configured to exclusive-OR the first PRBS and the second PRBS to compute a third PRBS. The system also includes an adder, a correlator and a corrector. The adder adds the third PRBS to input data to compute summed data for transmission of the summed data across the channel. The correlator computes the exclusive-OR of the first PRBS and the second PRBS to reproduce the third PRBS and correlates output data from the channel to the reproduced third PRBS to compute a channel gain error and a channel memory error. The corrector extracts the input data from the output data from the channel using the computed channel gain and memory errors.

公开(公告)号：US10673456B1

公开(公告)日：2020-06-02

申请号：US16410698

申请日：2019-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun Dusad ,  Chirag Chandrahas Shetty ,  Visvesvaraya Appala Pentakota

IPC: H03M1/50 ,  H03M1/14 ,  H03M1/20 ,  H03M1/44

Abstract: A conversion and folding circuit includes a voltage-to-delay converter block, including preamplifiers, for converting a voltage signal into delay signals, and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals. If desired, the logic gates may include odd and even chains for outputting delay signals to first and second analog-to-digital converters. If desired, the conversion and folding circuit may include first and second chains, and a chain selection circuit for selectively outputting a delay signal from a desired one of the first and second chains.

公开(公告)号：US10673453B1

公开(公告)日：2020-06-02

申请号：US16517796

申请日：2019-07-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Visvesvaraya Appala Pentakota ,  Rishi Soundararajan ,  Shagun Dusad ,  Chirag Chandrahas Shetty

IPC: H03M1/38 ,  H03K5/24 ,  H03K19/20 ,  H03M1/12 ,  H03M1/00 ,  H03M1/14

Abstract: An analog-to-digital converter has a logic gate for generating an output signal having a delay corresponding to a delay between input signals. The logic gate includes inputs for receiving the input signals, and an output for outputting the output signal. A delay comparator generates a digital signal representative of the order of the input signals, and generates a delay signal having a delay corresponding to the delay between the input signals. The delay comparator has inputs for receiving the input signals, a digital output for outputting the digital signal, and a delay output for outputting the delay signal. A delay-based analog-to-digital converter, with a front stage and successive residual stages, is also disclosed. A delay comparator having merged comparator, sign-out, and delay-out circuits, and which may be operated within one of successive stages, without a clock, is also disclosed.

公开(公告)号：US10425042B2

公开(公告)日：2019-09-24

申请号：US15859431

申请日：2017-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ani Xavier ,  Neeraj Shrivastava ,  Arun Mohan ,  Shagun Dusad

IPC: H03F3/45 ,  H03F1/30 ,  H03F1/02

Abstract: In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.