公开(公告)号：US20240395907A1

公开(公告)日：2024-11-28

申请号：US18790476

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US20240387729A1

公开(公告)日：2024-11-21

申请号：US18775341

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Han-Chi Lin ,  Chunyao Wang ,  Ching Yu Huang ,  Tze-Liang Lee ,  Yung-Chih Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

公开(公告)号：US12112988B2

公开(公告)日：2024-10-08

申请号：US18361566

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/82 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L21/28518 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76229 ,  H01L21/764 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.

公开(公告)号：US12112942B2

公开(公告)日：2024-10-08

申请号：US17818823

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/02 ,  C23C16/455 ,  H01L21/443 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/383

CPC classification number: H01L21/0228 ,  C23C16/45525 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L21/383 ,  H01L21/443

Abstract: A method includes placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate includes a trench, and performing an atomic layer deposition (ALD) process to deposit a dielectric material within the trench, including flowing a first precursor of the dielectric material into the deposition chamber as a gas phase; flowing a second precursor of the dielectric material into the deposition chamber as a gas phase; and controlling the pressure and temperature within the deposition chamber such that the second precursor condenses on surfaces within the trench as a liquid phase of the second precursor, wherein the liquid phase of the second precursor has capillarity.

公开(公告)号：US20240304496A1

公开(公告)日：2024-09-12

申请号：US18668960

申请日：2024-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Tai-Chun Huang ,  Jr-Hung Li ,  Tze-Liang Lee ,  Chi On Chui

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. The method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material in combination form a second fin isolation region.

公开(公告)号：US11837505B2

公开(公告)日：2023-12-05

申请号：US17813862

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L21/28518 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76229 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.

公开(公告)号：US11728173B2

公开(公告)日：2023-08-15

申请号：US17038499

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Wan-Chen Hsieh ,  Chun-Ming Lung ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/308 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/3085 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02356 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US20230116949A1

公开(公告)日：2023-04-20

申请号：US18068367

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Fong Lin ,  Wan Chen Hsieh ,  Chung-Ting Ko ,  Tai-Chun Huang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

公开(公告)号：US20220384649A1

公开(公告)日：2022-12-01

申请号：US17818595

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Han-Chi Lin ,  Chunyao Wang ,  Ching Yu Huang ,  Tze-Liang Lee ,  Yung-Chih Wang

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/3065 ,  H01L27/088 ,  H01L21/8234

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

公开(公告)号：US20220367187A1

公开(公告)日：2022-11-17

申请号：US17353380

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Sung-En Lin ,  Chi On Chui

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66

Abstract: Structures and methods of forming semiconductor devices are presented in which a void-free core-shell hard mask is formed over a gate electrode. The void-free core-shell hard mask may be formed in some embodiments by forming a first liner layer over the gate electrode, forming a void-free material over the first liner layer, recessing the void-free material, and forming a second liner over the recessed void-free material.