公开(公告)号：US09000536B2

公开(公告)日：2015-04-07

申请号：US13930242

申请日：2013-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Kuo ,  Hou-Yu Chen ,  Shyh-Horng Yang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66803

Abstract: The present disclosure relates a Fin field effect transistor (FinFET) device having large effective oxide thickness that mitigates hot carrier injection, and an associated method of formation. In some embodiments, the FinFET device has a conductive channel of a first fin protruding from a planar substrate. The conductive channel has a non-conductive highly doped region located along multiple outer edges of the channel region. A gate region protrudes from the planar substrate as a second fin that overlies the first fin. A gate dielectric region is located between the non-conductive highly doped region and the gate region. The non-conductive highly doped region and the gate dielectric region collectively provide for an effective oxide thickness of the FinFET device that allow a low electric field across gate oxide and less hot carrier injection.

Abstract translation: 本公开内容涉及具有大的有效氧化物厚度的Fin场效应晶体管（FinFET）器件，其减轻热载流子注入，以及相关联的形成方法。 在一些实施例中，FinFET器件具有从平面衬底突出的第一鳍片的导电沟道。 导电通道具有沿通道区域的多个外边缘定位的非导电高度掺杂区域。 栅极区域作为覆盖在第一鳍片上的第二鳍片从平面衬底突出。 栅极电介质区域位于非导电高掺杂区域和栅极区域之间。 非导电高掺杂区域和栅极电介质区域共同地提供FinFET器件的有效氧化物厚度，其允许跨栅极氧化物和较少热载流子注入的低电场。

公开(公告)号：US20250120166A1

公开(公告)日：2025-04-10

申请号：US18982010

申请日：2024-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

公开(公告)号：US12170231B2

公开(公告)日：2024-12-17

申请号：US17815079

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

公开(公告)号：US12166016B2

公开(公告)日：2024-12-10

申请号：US18446626

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yi Chuang ,  Hou-Yu Chen ,  Kuan-Lun Cheng

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L25/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

Abstract: Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

公开(公告)号：US20240250142A1

公开(公告)日：2024-07-25

申请号：US18623285

申请日：2024-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Yi-Bo Liao ,  Hou-Yu Chen ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L21/306 ,  H01L21/311 ,  H01L21/321 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.

公开(公告)号：US11837535B2

公开(公告)日：2023-12-05

申请号：US17812887

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chung-Hui Chen

IPC: H01L23/522 ,  H01L21/84 ,  H01L23/528 ,  H01L23/532 ,  H01L27/12 ,  H01L21/768 ,  H01L21/8238 ,  G11C11/22

CPC classification number: H01L23/5223 ,  H01L21/845 ,  H01L23/5286 ,  H01L23/5329 ,  H01L27/1211 ,  G11C11/221 ,  H01L21/7681 ,  H01L21/823821 ,  H01L23/528

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

公开(公告)号：US20230386993A1

公开(公告)日：2023-11-30

申请号：US18446648

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chung-Hui Chen

IPC: H01L23/522 ,  H01L21/84 ,  H01L27/12 ,  H01L23/528 ,  H01L23/532 ,  G11C11/22 ,  H01L21/768 ,  H01L21/8238

CPC classification number: H01L23/5223 ,  H01L21/845 ,  H01L27/1211 ,  H01L23/5286 ,  H01L23/5329 ,  G11C11/221 ,  H01L21/7681 ,  H01L21/823821 ,  H01L23/528

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

公开(公告)号：US11574907B2

公开(公告)日：2023-02-07

申请号：US17170601

申请日：2021-02-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chang Lin ,  Chun-Feng Nieh ,  Huicheng Chang ,  Hou-Yu Chen ,  Yong-Yan Lu

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L29/49 ,  H01L29/165 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/84

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

公开(公告)号：US11532720B2

公开(公告)日：2022-12-20

申请号：US16996094

申请日：2020-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Hou-Yu Chen ,  Ching-Wei Tsai

IPC: H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor layer, a gate structure, a source/drain epitaxial structure, a backside dielectric cap, and an inner spacer. The gate structure wraps around the semiconductor layer. The source/drain epitaxial structure is adjacent the gate structure and electrically connected to the semiconductor layer. The backside dielectric cap is disposed under and in direct contact with the gate structure. The inner spacer is in direct contact with the gate structure and the backside dielectric cap.

公开(公告)号：US20220165885A1

公开(公告)日：2022-05-26

申请号：US17671156

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Pei-Yu Wang ,  Cheng-Ting Chung ,  Ching-Wei Tsai ,  Hou-Yu Chen

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.