公开(公告)号：US20240063208A1

公开(公告)日：2024-02-22

申请号：US17892344

申请日：2022-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Yen Lee ,  Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shin-Puu Jeng

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L24/19 ,  H01L21/4857 ,  H01L25/0655 ,  H01L24/81 ,  H01L24/83 ,  H01L24/20 ,  H01L21/561 ,  H01L24/32 ,  H01L24/16 ,  H01L23/49833 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/95 ,  H01L24/92 ,  H01L24/73 ,  H01L21/568 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/81815 ,  H01L2224/16238 ,  H01L2224/83102 ,  H01L2224/32225 ,  H01L23/49894 ,  H01L2224/92125 ,  H01L2224/73204 ,  H01L2224/95001

Abstract: A method includes forming a first redistribution structure over a carrier, where forming the first redistribution structure includes forming a plurality of first organic polymer layers over the carrier, and forming a plurality of first conductive lines in the plurality of first organic polymer layers, attaching a first package structure to the first redistribution structure, the first package structure including a first semiconductor die, a molding material that surrounds an entirety of a perimeter of the first semiconductor die, and a second redistribution structure on bottom surfaces of the first semiconductor die and the molding material, dispensing a first underfill into a first gap between the plurality of first conductive lines and the first package structure, bonding a substrate to the first redistribution structure using first conductive connectors, and dispensing a second underfill into a second gap between the substrate and the first redistribution structure.

公开(公告)号：US20230387063A1

公开(公告)日：2023-11-30

申请号：US17664689

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Lin ,  Shu-Shen Yeh ,  Ming-Chih Yew ,  Chin-Hua Wang ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L24/32 ,  H01L24/27 ,  H01L25/0655 ,  H01L23/49833 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/26155 ,  H01L2224/3201 ,  H01L2224/27013 ,  H01L2924/1436 ,  H01L2924/1431 ,  H01L23/49838 ,  H01L23/49822 ,  H01L23/49816

Abstract: A package includes a package substrate, the package substrate having a first side and a second side opposite to the first side, a package component bonded to the first side of the package substrate, a front-side warpage control structure attached to the first side of the package substrate, and a backside warpage control structure embedded in the package substrate from the second side of the package substrate. The front-side warpage control structure includes a first disconnected structure and a second disconnected structure laterally separated from each other by a gap. The backside warpage control structure includes a third disconnected structure and a fourth disconnected structure laterally separated from each other.

公开(公告)号：US20230378092A1

公开(公告)日：2023-11-23

申请号：US17663692

申请日：2022-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chen Lai ,  Ming-Chih Yew ,  Shin-Puu Jeng ,  Yu-Sheng Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L25/0655 ,  H01L24/73 ,  H01L24/32 ,  H01L24/16 ,  H01L25/50 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2224/73204 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2924/1711 ,  H01L2924/172

Abstract: A semiconductor package including a recessed stiffener ring and a method of forming are provided. The semiconductor package may include a substrate, a semiconductor die bonded to the substrate, an underfill between the semiconductor die and the substrate, and a stiffener ring attached to the substrate, wherein the stiffener ring encircles the semiconductor die in a top view. The stiffener ring may include a recess that faces the semiconductor die.

公开(公告)号：US20220328392A1

公开(公告)日：2022-10-13

申请号：US17808827

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.

公开(公告)号：US20220139860A1

公开(公告)日：2022-05-05

申请号：US17178460

申请日：2021-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tsung-Yen Lee ,  Chia-Kuei Hsu ,  Shang-Lun Tsai ,  Ming-Chih Yew ,  Po-Yao Lin

IPC: H01L23/00 ,  H01L25/065

Abstract: A method includes forming a package component comprising forming a dielectric layer, patterning the dielectric layer to form an opening, and forming a redistribution line including a via in the opening, a conductive pad, and a bent trace. The via is vertically offset from the conductive pad. The conductive pad and the bent trace are over the dielectric layer. The bent trace connects the conductive pad to the via, and the bent trace includes a plurality of sections with lengthwise directions un-parallel to each other. A conductive bump is formed on the conductive pad.

公开(公告)号：US11201142B2

公开(公告)日：2021-12-14

申请号：US15660968

申请日：2017-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Ming-Chih Yew ,  Yi-Jen Lai ,  Ming-Shih Yeh

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/544 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31 ,  H01L23/50 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

公开(公告)号：US20210335753A1

公开(公告)日：2021-10-28

申请号：US17028629

申请日：2020-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Che-Chia Yang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

公开(公告)号：US10685920B2

公开(公告)日：2020-06-16

申请号：US15823474

申请日：2017-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Chih Yew ,  Fu-Jen Li ,  Po-Yao Lin ,  Kuo-Chuan Liu

IPC: H01L23/00 ,  H01L23/36 ,  H01L23/40 ,  H01L23/31

Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.