公开(公告)号：US20210375760A1

公开(公告)日：2021-12-02

申请号：US17402897

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Lun Kao ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Jian-Hua Chen ,  Yu-Chieh Liao ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/768 ,  H01L21/263 ,  H01L23/532

Abstract: A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.

公开(公告)号：US11069811B2

公开(公告)日：2021-07-20

申请号：US16548423

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/308

Abstract: A method for forming a semiconductor device structure is provided. The method for forming the semiconductor device structure includes forming a first mask layer covering the gate stack, forming a contact alongside the gate stack and the first mask layer, recessing the contact, etching the first mask layer, and forming a second mask layer covering the contact and a portion of the first mask layer.

公开(公告)号：US11043594B2

公开(公告)日：2021-06-22

申请号：US16441107

申请日：2019-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

公开(公告)号：US20210082742A1

公开(公告)日：2021-03-18

申请号：US16573719

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L23/532

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

公开(公告)号：US10833152B2

公开(公告)日：2020-11-10

申请号：US15677089

申请日：2017-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tien-Lu Lin ,  Jung-Hung Chang

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/84 ,  H01L29/10

Abstract: A semiconductor device includes a substrate, a liner, and an isolation structure. The substrate has at least one first semiconductor fin and at least one second semiconductor fin. The liner is disposed on at least one sidewall of the second semiconductor fin. The isolation structure is disposed over the substrate, in which the isolation structure is in contact with the first semiconductor fin and the liner.

公开(公告)号：US10700005B2

公开(公告)日：2020-06-30

申请号：US16394483

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first metal wire arranged within an inter-level dielectric (ILD) layer over a substrate and laterally separated in a first direction from a first closest air-gap by a first distance. A second metal wire is arranged within the ILD layer and is laterally separated in the first direction from a second closest air-gap by a second distance that is larger than the first distance. A via is disposed on an upper surface of the second metal wire.

公开(公告)号：US09559134B2

公开(公告)日：2017-01-31

申请号：US14564196

申请日：2014-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Jung-I Lin ,  Ta-Chun Lin ,  Tien-Lu Lin ,  Chen-Jong Wang

IPC: H01L27/148 ,  H01L29/768 ,  H01L29/00 ,  H01L27/146 ,  H01L27/092 ,  H01L29/94 ,  H01L27/12

CPC classification number: H01L21/764 ,  H01L21/76224 ,  H01L21/76227 ,  H01L21/76289 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/0921 ,  H01L27/1203 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14689 ,  H01L29/945

Abstract: An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate. A trench is arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, and the trench has a gap located between sidewalls of the trench. A cap is arranged over or within the trench at a position overlying the gap. The cap seals the gap within the trench. A method of manufacturing the image sensor is also provided.

Abstract translation: 提供了采用深沟槽间隔隔离的图像传感器。 多个像素传感器布置在半导体衬底之上或之内。 沟槽在多个像素传感器周围和相邻的像素传感器之间并且在半导体衬底中布置，并且沟槽在沟槽的侧壁之间具有间隙。 在覆盖间隙的位置处，在沟槽之上或之内布置盖。 盖子密封沟槽内的间隙。 还提供了一种制造图像传感器的方法。

公开(公告)号：US20160284593A1

公开(公告)日：2016-09-29

申请号：US15170059

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method of forming an interconnect structure. In some embodiments, the method is performed by forming a trench within a first dielectric layer and forming sacrificial spacers along sidewalls of the trench. The trench is filled with a conductive material, and the sacrificial spacers are removed after the trench has been filled with the conductive material. A second dielectric layer is formed over the first dielectric layer to leave an air-gap in a region from which the sacrificial spacers were removed.

Abstract translation: 本公开涉及一种形成互连结构的方法。 在一些实施例中，该方法通过在第一介电层内形成沟槽并沿着沟槽的侧壁形成牺牲间隔来执行。 沟槽填充有导电材料，并且在沟槽填充有导电材料之后去除牺牲隔离物。 在第一电介质层上方形成第二电介质层，以在除去牺牲间隔物的区域中留下气隙。

公开(公告)号：US09412652B2

公开(公告)日：2016-08-09

申请号：US14739413

申请日：2015-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Tien Wu ,  Tien-Lu Lin

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02178 ,  H01L21/02258 ,  H01L21/76807 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to obtain an alumina dielectric layer with a plurality of pores. The openings are filled with a conductive interconnect material. The pores are widened to form air gaps and a top etch stop layer is formed over the alumina dielectric layer.

Abstract translation: 在半导体衬底上形成铝（Al）层。 去除Al层的选择性部分以形成开口。 将Al层进行阳极氧化，得到具有多个孔的氧化铝介电层。 开口填充有导电互连材料。 孔被加宽以形成气隙，并且在氧化铝介质层上形成顶部蚀刻停止层。

公开(公告)号：US12131942B2

公开(公告)日：2024-10-29

申请号：US18344965

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/762 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L21/76224 ,  H01L21/31144 ,  H01L27/0886

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.