公开(公告)号：US10163805B2

公开(公告)日：2018-12-25

申请号：US15200747

申请日：2016-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683

Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate and a package layer formed over the substrate. The package structure further includes an alignment structure formed over the package layer, and the alignment structure includes a first alignment mark formed in a trench, and the trench has a step-shaped structure.

公开(公告)号：US09093176B2

公开(公告)日：2015-07-28

申请号：US13674192

申请日：2012-11-12

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Wei-Cheng Wu ,  Wei Min Chan ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C11/419 ,  G11C11/4197

CPC classification number: G11C11/419

Abstract: Some embodiments of the present disclosure relate to a memory array having a cell voltage generator configured to provide a cell voltage header to a plurality of memory cells. The cell voltage generator is connected to the memory cells by way of supply voltage line and controls a supply voltage of the memory cells. The cell voltage generator has a pull-down element coupled between a control node of the supply voltage line and a ground terminal, and a one or more pull-up elements connected in parallel between the control node and a cell voltage source. A control unit is configured to provide one or more variable valued pull-up enable signals to input nodes of the pull-up elements. The variable valued pull-up enable signals operate the pull-up elements to selectively connect the supply voltage line from the cell voltage source to provide a cell voltage header with a high slew rate.

Abstract translation: 本公开的一些实施例涉及具有单元电压发生器的存储器阵列，其被配置为向多个存储器单元提供单元电压报头。 电池电压发生器通过电源电压线连接到存储器单元，并控制存储器单元的电源电压。 电池电压发生器具有耦合在电源电压线的控制节点和接地端子之间的下拉元件以及在控制节点和电池电压源之间并联连接的一个或多个上拉元件。 控制单元被配置为向上拉元件的输入节点提供一个或多个可变值上拉使能信号。 可变值上拉使能信号操作上拉元件以选择性地将电源电压线与电池电压源连接，以提供具有高压摆率的电池电压头。

公开(公告)号：US20250167161A1

公开(公告)日：2025-05-22

申请号：US18585854

申请日：2024-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jin Hu ,  Hua-Wei Tseng ,  Wei-Cheng Wu ,  Yung-Ping Chiang ,  An-Jhih Su ,  Der-Chyang Yeh

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

Abstract: A package includes a first die over and bonded to a first side of a package component, where a first bond between the first die and the package component includes a dielectric-to-dielectric bond between a first bonding layer of the first die and a second bonding layer on the package component, and second bonds between the first die and the package component include metal-to-metal bonds between first bonding pads of the first die and second bonding pads on the package component, a first portion of a redistribution structure adjacent to the first die and over the second bonding layer, and a second die over and coupled to the first portion of the redistribution structure using first conductive connectors, where the first conductive connectors are electrically connected to first conductive pads in the second bonding layer.

公开(公告)号：US20250125223A1

公开(公告)日：2025-04-17

申请号：US18415426

申请日：2024-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Ta-Hsuan Lin ,  Hua-Wei Tseng ,  Wei-Cheng Wu

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes forming a metal pad, depositing a passivation layer on the metal pad, and planarizing the passivation layer, so that the passivation layer includes a planar top surface. The method further includes etching the passivation layer to form an opening in the passivation layer, wherein the metal pad is exposed to the opening, and forming a conductive via including a lower portion in the opening, and an upper portion higher than the passivation layer. A polymer layer is then dispensed to cover the conductive via.

公开(公告)号：US12217975B2

公开(公告)日：2025-02-04

申请号：US18527151

申请日：2023-12-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Alexander Kalnitsky ,  Wei-Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H01L29/78 ,  H01L21/321 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.

公开(公告)号：US11854828B2

公开(公告)日：2023-12-26

申请号：US17850643

申请日：2022-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Alexander Kalnitsky ,  Wei-Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H01L21/8234 ,  H01L21/321 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L21/3212 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/4916 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/7816

Abstract: A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.

公开(公告)号：US11652063B2

公开(公告)日：2023-05-16

申请号：US16927126

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Tsung-Shu Lin

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.

公开(公告)号：US11508695B2

公开(公告)日：2022-11-22

申请号：US17195903

申请日：2021-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.

公开(公告)号：US20220361332A1

公开(公告)日：2022-11-10

申请号：US17815373

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Hsieh ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Li-Han Hsu ,  Wei-Cheng Wu

IPC: H05K1/11 ,  H01L23/00 ,  H05K1/18

Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

公开(公告)号：US20220359470A1

公开(公告)日：2022-11-10

申请号：US17815390

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Wei-Yu Chen ,  Ying-Ju Chen ,  Tsung-Shu Lin ,  Chin-Chuan Chang ,  Hsien-Wei Chen ,  Wei-Cheng Wu ,  Li-Hsien Huang ,  Chi-Hsi Wu ,  Der-Chyang Yeh

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.