公开(公告)号：US20110310666A1

公开(公告)日：2011-12-22

申请号：US13203612

申请日：2009-04-30

申请人： Takashi Miida ,  Riichiro Shirota ,  Hideki Arakawa ,  Ching Sung Yang ,  Tzung Ling Lin

发明人： Takashi Miida ,  Riichiro Shirota ,  Hideki Arakawa ,  Ching Sung Yang ,  Tzung Ling Lin

IPC分类号： G11C16/10

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/102 ,  G11C16/3418 ,  H01L27/11524 ,  H01L27/11526

摘要： In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.

摘要翻译： 在NAND闪速存储器件的编程方法中，使用自增强方案来消除否则会导致编程干扰的抑制单元串的通道中的多余电子。 在增强通道之前，通过对连接到禁止单元串的字线施加负电压来实现消除，并且这导致高程序抗扰性。 还描述了实现编程操作的行解码器电路和基于编程方案的文件系统架构以提高文件管理的效率。

公开(公告)号：US20080042230A1

公开(公告)日：2008-02-21

申请号：US11465815

申请日：2006-08-21

申请人： Takashi Miida

发明人： Takashi Miida

IPC分类号： H01L31/00 ,  H01L21/00

CPC分类号： H01L31/105 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/14632

摘要： An image sensor has a substrate, a dielectric layer positioned on the substrate, a pixel array including a plurality of pixels defined on the substrate, a shield electrode positioned between any two adjacent pixel electrodes of the pixels, a photo conductive layer positioned on the shield electrode and the pixel electrodes, and a transparent conductive layer covering the photo conductive layer.

摘要翻译： 图像传感器具有衬底，位于衬底上的电介质层，包括限定在衬底上的多个像素的像素阵列，位于像素的任意两个相邻像素电极之间的屏蔽电极，位于屏蔽层上的光电导层 电极和像素电极，以及覆盖光电导层的透明导电层。

公开(公告)号：US07279384B2

公开(公告)日：2007-10-09

申请号：US11283984

申请日：2005-11-22

申请人： Takashi Miida

发明人： Takashi Miida

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7887

摘要： A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a P type silicon substrate, a control gate CG and a pair of electrically isolated floating gates. Plural projections are formed in the silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate extending in the row direction faces the projection and the floating gate FG1, FG2 via an insulation layer. The width W1 of the floating gate FG1, FG2 in the column direction is larger than the width W2 of the control gate CG, so the floating gate FG1, FG2 and the control gate CG can be manufactured without the self-align process.

摘要翻译： 半导体存储器具有以矩阵排列的多个单元晶体管。 单元晶体管包括P型硅衬底，控制栅极CG和一对电隔离的浮动栅极。 在硅衬底中形成多个突起，并且在突起的两侧形成作为源极和漏极的一对N型扩散区域。 在行方向延伸的控制栅极经由绝缘层面对突起和浮置栅极FG 1，FG 2。 浮动栅极FG 1的宽度W 1，列方向上的FG 2大于控制栅极CG的宽度W 2，因此浮动栅极FG 1，FG 2和控制栅极CG可以在没有自身的情况下制造 对齐过程。

公开(公告)号：US20050190605A1

公开(公告)日：2005-09-01

申请号：US11053952

申请日：2005-02-10

申请人： Takashi Miida

发明人： Takashi Miida

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  H01L27/115 ,  H01L29/7887

摘要： A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a silicon substrate, a control gate, a pair of electrically isolated floating gates. Plural projections are formed in the P type silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate faces the projection via a fourth insulation layer. The side surface of the floating gates faces the side surfaces of the projection via a first insulation layer, and faces the control gate via a third insulation layer. The floating gate faces the diffusion region via the first insulation layer.

摘要翻译： 半导体存储器具有以矩阵排列的多个单元晶体管。 单元晶体管包括硅衬底，控制栅极，一对电隔离的浮动栅极。 在P型硅衬底中形成多个突起，并且在突起的两侧形成作为源极和漏极的一对N型扩散区域。 控制门通过第四绝缘层面向突出部。 浮动栅极的侧表面经由第一绝缘层面对突起的侧表面，并且经由第三绝缘层面对控制栅极。 浮栅经由第一绝缘层面向扩散区。

公开(公告)号：US06812518B2

公开(公告)日：2004-11-02

申请号：US10285540

申请日：2002-11-01

申请人： Takashi Miida

发明人： Takashi Miida

IPC分类号： H10L29788

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/66825 ,  H01L29/7887

摘要： A multiple-bit cell transistor includes a P type silicon substrate, agate insulation layer, a pair of N type source/drain regions, a pair of tunnel insulation layers, and a pair of floating gates. The silicon substrate is formed with a projection while the floating gates each are positioned on one of opposite side walls of the projection. Inter-polycrystalline insulation layers each are formed on one of the floating gates. A control gate faces the top of the projection via the gate insulation layer. An N type region is formed on each side of the projection and contacts the source/drain region adjoining it. The cell transistor lowers a required write voltage, broadens a current window, and enhances resistance to inter-band tunneling.

摘要翻译： 多位单元晶体管包括P型硅衬底，玛瑙绝缘层，一对N型源极/漏极区，一对隧道绝缘层和一对浮动栅极。 硅衬底形成有突起，而浮栅各自位于突起的相对侧壁中的一个上。 多晶硅绝缘层各自形成在一个浮动栅极上。 控制门通过栅极绝缘层面向突起的顶部。 N型区域形成在突起的每一侧上，并与其邻接的源极/漏极区域接触。 单元晶体管降低了所需的写入电压，拓宽了当前窗口，并增强了对带内隧道效应的阻力。

公开(公告)号：US06768093B2

公开(公告)日：2004-07-27

申请号：US10238638

申请日：2002-09-11

申请人： Takashi Miida

发明人： Takashi Miida

IPC分类号： H01J4014

CPC分类号： H01L27/14609 ,  H01L27/14623 ,  H01L27/14643 ,  H04N5/374

摘要： Disclosed is a solid state imaging device, comprising a unit pixel 101 including a photo diode 111 and a MOS transistor 112 for optical signal detection provided with a high-density buried layer 25 for storing optically generated charges generated by light irradiation in the photo diode 111, a vertical scanning signal driving scanning circuit 102 for outputting a scanning signal to a gate electrode 19, and a voltage boost scanning circuit 108 for outputting a boosted voltage higher than a power source voltage to a source region 16. In this case, a boosted voltage is applied from the voltage boost scanning circuit 108 to the source region 16, and the optically generated charges stored in the high-density buried layer 25 are swept out from the high-density buried layer 25 by a source voltage and a gate voltage risen by the boosted voltage.

摘要翻译： 公开了一种固态成像装置，其包括单元像素101，其包括光电二极管111和用于光信号检测的MOS晶体管112，其具有用于存储光电二极管111中由光照射产生的光学产生的电荷的高密度掩埋层25 ，用于向栅极电极19输出扫描信号的垂直扫描信号驱动扫描电路102以及用于将高于电源电压的升压电压输出到源极区域16的升压扫描电路108.在这种情况下， 从升压扫描电路108向源极区域16施加电压，并且通过源极电压和栅极电压上升从高密度掩埋层25扫出存储在高密度掩埋层25中的光学产生的电荷 通过升压电压。

公开(公告)号：US06747264B2

公开(公告)日：2004-06-08

申请号：US10074227

申请日：2002-02-14

申请人： Takashi Miida

发明人： Takashi Miida

IPC分类号： H01J4014

CPC分类号： H04N5/361 ,  H01L27/14609 ,  H03G3/3084 ,  H04N5/335

摘要： A solid-state imaging device is provided, which is capable of increasing an S/N ratio while enhancing a dynamic range, when a photoelectric signal is converted into a digital signal. This solid-state imaging device comprises: a plurality of photoelectric conversion devices arrayed in rows and columns, each of the photoelectric conversion devices converting an optical signal into an electric signal and outputting a first signal voltage; a difference signal generation circuit provided for each column, for sequentially inputting the first signal voltage and a second signal voltage obtained by initializing the photoelectric conversion devices, thereafter converting the first signal voltage and the second signal voltage into charges, generating a difference signal therebetween, and then outputting the difference signal after adjusting a gain according to a level of the difference signal; and an analog/digital conversion circuit connected to the output of the difference signal generation circuit.

摘要翻译： 提供了一种固态成像装置，当光电信号被转换为数字信号时，能够增加S / N比，同时增强动态范围。 该固态成像装置包括：以行和列排列的多个光电转换装置，每个光电转换装置将光信号转换为电信号并输出​​第一信号电压; 为每列设置的差分信号生成电路，用于依次输入第一信号电压和通过初始化光电转换装置获得的第二信号电压，之后将第一信号电压和第二信号电压转换为电荷，在其间产生差分信号， 然后根据差分信号的电平调整增益后输出差分信号; 以及连接到差分信号发生电路的输出的模拟/数字转换电路。

公开(公告)号：US06538925B2

公开(公告)日：2003-03-25

申请号：US09984190

申请日：2001-10-29

申请人： Takashi Miida

发明人： Takashi Miida

IPC分类号： G11C1134

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： The present invention relates to a dual bit nonvolatile programmable read/write memory containing a semiconductor memory element having one conductivity type semiconductor substrate including at least one convex portion. A pair of opposite conductivity source/drain regions are formed on a surface of the semiconductor substrate an opposing sides of the convex portion, and a first insulating film covers the upper surface of the convex portion. Second insulating films cover the side surfaces of the convex portion and the source/drain regions. A pair of floating gates abut opposing side surfaces of the convex portion and the source/drain regions through the second insulating films. Third insulating films are formed on the floating gates. A control gate covers the upper surface of the convex portion through the first insulating film and the floating gates through the third insulating films.

摘要翻译： 本发明涉及一种包含半导体存储元件的双位非易失性可编程读/写存储器，其具有包括至少一个凸部的一导电型半导体衬底。 在半导体衬底的表面上形成一对相反的导电源极/漏极区域，该凸起部分的相对侧面，并且第一绝缘膜覆盖凸部的上表面。 第二绝缘膜覆盖凸部和源极/漏极区的侧表面。 一对浮动栅极通过第二绝缘膜与凸起部分和源极/漏极区域相对的侧表面相邻。 在浮栅上形成第三绝缘膜。 控制栅极通过第一绝缘膜和通过第三绝缘膜的浮栅覆盖凸部的上表面。

公开(公告)号：US06051857A

公开(公告)日：2000-04-18

申请号：US192529

申请日：1998-11-17

申请人： Takashi Miida

发明人： Takashi Miida

IPC分类号： H01L27/146 ,  H04N5/355 ,  H01L31/062 ,  H01L31/113

CPC分类号： H04N5/35518 ,  H01L27/14609 ,  H01L27/14679

摘要： The present invention is a method for detecting photo signals using an imaging device, comprising steps of photo-generating holes in a well region 15 of a photo-diode by a signal light, transferring the photo-generated holes through a bulk of the well region 15 to a heavily doped buried layer 25 which is formed in the well region 15 near a source region 16 by doping that region with impurity heavier than the well region (15) of an insulated gate FET, storing the photo-generated holes in the heavily doped buried layer 25 to thereby change the threshold of the FET corresponding to the amount of the photo-generated charge, and reading the change in the threshold as the amount of signal light received by the photo-sensor.

公开(公告)号：US5115155A

公开(公告)日：1992-05-19

申请号：US685773

申请日：1991-04-16

申请人： Takashi Miida ,  Yoshimitsu Kudoh ,  Hiedki Mutoh

发明人： Takashi Miida ,  Yoshimitsu Kudoh ,  Hiedki Mutoh

IPC分类号： H01L21/339 ,  G11C19/28 ,  G11C27/04 ,  H01L29/762 ,  H03M1/66

CPC分类号： G11C19/285 ,  G11C27/04

摘要： A charge-coupled device (CCD) delay line having a temperature compensation circuit capable of compensating for temperature variations for providing an accurate and consistent delay of an input signal. The temperature compensation circuit includes first and second registers for transferring charges, and a sample-and-hold circuit connected between outputs of each register and two inputs of a differential amplifier. The differential amplifier supplies a signal which corresponds to temperature variations to properly bias the input signal.

摘要翻译： 一种具有温度补偿电路的电荷耦合器件（CCD）延迟线，其能够补偿温度变化，以提供输入信号的精确和一致的延迟。 温度补偿电路包括用于传送电荷的第一和第二寄存器，以及连接在每个寄存器的输出和差分放大器的两个输入端之间的采样和保持电路。 差分放大器提供对应于温度变化的信号以适当地偏置输入信号。