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    Data processor and data processor system having multiple modes of address indexing and operation
    42.
    发明授权
    Data processor and data processor system having multiple modes of address indexing and operation 有权
    数据处理器和数据处理器系统具有多种地址索引和操作模式

    公开(公告)号：US06532528B1

    公开(公告)日：2003-03-11

    申请号：US09563753

    申请日：2000-05-01

    申请人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

    发明人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

    IPC分类号： G06F1210

    CPC分类号： G06F12/1027 ,  G06F2212/652

    摘要： A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

    摘要翻译： 公开了一种提高地址转换操作速度的数据处理器。 翻译后备缓冲区被分为用于数据的缓冲器和用于指令的缓冲器，用于指令的地址转换信息也被存储到用于数据的翻译后备缓冲器中，并且当用于指令的翻译后备缓冲器中发生翻译错误时，新的地址转换 从数据的翻译后备缓冲区中提取信息。 与每次在用于指令的翻译后备缓冲器中发生翻译缺口时从外部地址转换表获得地址转换信息的情况相比，可以实现地址转换操作的高速度。

    Semiconductor integrated circuit device
    44.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US06436741B2

    公开(公告)日：2002-08-20

    申请号：US09822429

    申请日：2001-04-02

    申请人： Masayuki Sato ,  Kunio Uchiyama

    发明人： Masayuki Sato ,  Kunio Uchiyama

    IPC分类号： H01L2100

    CPC分类号： G11C29/12 ,  G11C2029/0401 ,  G11C2029/1206

    摘要： A logic test having less over-head for testing a logic circuit in a chip is implemented by constituting a test circuit in the chip without introducing a novel device process of FPGA. A memory of a self-configuration type is provided in the chip and a test circuit is constituted in the memory of a self-configuration type or an ordinary memory through a tester HDL, thereby testing other memories and logic circuits in the chip. The test circuit is reconstituted such that the memory used in the structure of the test circuit can be operated as an ordinary memory.

    摘要翻译： 通过在芯片中构成测试电路而不引入FPGA的新颖的器件处理来实现具有用于测试芯片中的逻辑电路的较少过载的逻辑测试。 在芯片中提供自配置型存储器，并且通过测试器HDL在自配置型或普通存储器的存储器中构成测试电路，从而测试芯片中的其他存储器和逻辑电路。 测试电路被重构，使得在测试电路的结构中使用的存储器可以作为普通存储器来操作。

    Data processor
    45.
    发明授权
    Data processor 失效
    数据处理器

    公开(公告)号：US5974533A

    公开(公告)日：1999-10-26

    申请号：US113550

    申请日：1998-07-10

    申请人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    发明人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/345 ,  G06F9/38 ,  G06F9/445 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F13/16 ,  G06F15/78

    CPC分类号： G06F9/30047 ,  G06F12/0848 ,  G06F12/0891 ,  G06F9/30043 ,  G06F9/3802 ,  G06F9/3824

    摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

    摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器还具有要执行的输出指令。 指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。

    Data processor having logical address memories and purge capabilities
    46.
    发明授权
    Data processor having logical address memories and purge capabilities 失效
    数据处理器具有逻辑地址存储器和清除功能

    公开(公告)号：US5349672A

    公开(公告)日：1994-09-20

    申请号：US503128

    申请日：1990-04-03

    申请人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    发明人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F9/00

    CPC分类号： G06F9/3802 ,  G06F12/0848 ,  G06F12/0891 ,  G06F9/3824

    摘要： A data processor is used with a main memory that stores operand data and instructions. The data processor itself includes two cache memories, one of which stores logical instruction addresses and corresponding instructions while the other stores logical operand addresses and corresponding operand data. A selector chooses whether a logical operand address or logical instruction address should access the respective cache memory or the main memory to obtain an instruction or operand data. Furthermore, the processor includes the capability of invalidating all of the data in either the instruction cache memory or operand cache memory based on a software instruction signal received at a purge unit.

    摘要翻译： 数据处理器与存储操作数数据和指令的主存储器一起使用。 数据处理器本身包括两个高速缓冲存储器，其中之一存储逻辑指令地址和对应的指令，而另一个存储逻辑操作数地址和相应的操作数数据。 选择器选择逻辑操作数地址或逻辑指令地址是否应该访问相应的高速缓冲存储器或主存储器以获得指令或操作数据。 此外，处理器包括基于在清除单元处接收的软件指令信号使指令高速缓冲存储器或操作数高速缓冲存储器中的所有数据无效的能力。

    Content addressable memory having dual access modes
    48.
    发明授权
    Content addressable memory having dual access modes 失效
    具有双重访问模式的内容可寻址存储器

    公开(公告)号：US4646271A

    公开(公告)日：1987-02-24

    申请号：US683611

    申请日：1984-12-19

    申请人： Kunio Uchiyama ,  Tadahiko Nishimukai

    发明人： Kunio Uchiyama ,  Tadahiko Nishimukai

    IPC分类号： G11C15/04 ,  G11C13/00

    CPC分类号： G11C15/04

    摘要： In a memory device having a content addressable memory array and a random access memory array, the word coincidence lines and word selection lines of the content addressable memory array are connected to the word selection lines of the corresponding words of the random access memory array via a selection circuit, access is made to the random access memory array on the basis of the result of association of the content addressable memory array when the selection circuit selects the word coincidence lines, and access is made to the memory device as a whole as a random access memory array when the selection circuit selects the word selection lines.

    摘要翻译： 在具有内容可寻址存储器阵列和随机存取存储器阵列的存储器件中，内容可寻址存储器阵列的单词一致线和字选择线经由一个随机存取存储器阵列的对应字的单词选择线经由 选择电路，当选择电路选择字符符合线时，基于内容可寻址存储器阵列的关联结果对随机存取存储器阵列进行访问，并且作为整体对存储器件进行随机访问 当选择电路选择字选择线时，存取存储器阵列。

    Substrate bias switching unit for a low power processor
    50.
    发明授权
    Substrate bias switching unit for a low power processor 有权
    用于低功耗处理器的基板偏置开关单元

    公开(公告)号：US07475261B2

    公开(公告)日：2009-01-06

    申请号：US10768136

    申请日：2004-02-02

    申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

    摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

    摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。