公开(公告)号：US20060286741A1

公开(公告)日：2006-12-21

申请号：US11154431

申请日：2005-06-16

申请人： Shanjen Pan ,  Sameer Pendharkar ,  Pinghai Hao ,  James Todd

发明人： Shanjen Pan ,  Sameer Pendharkar ,  Pinghai Hao ,  James Todd

IPC分类号： H01L21/8244

CPC分类号： H01L27/0629 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835

摘要： Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

摘要翻译： 制造方法和器件包括在电容器形成期间形成的场板。 在半导体衬底中形成隔离结构。 在半导体衬底中形成阱区。 在阱区域中形成漏极延伸区域。 在器件上形成栅极电介质层。 形成用作栅电极和底电容器板的栅极电极层。 对栅极电极和栅极介电层进行图案化以形成栅极结构。 源区和漏区形成在阱区和漏极延伸区内。 形成也用作电容器电介质的硅化物阻挡层。 在阻挡层上形成场板和顶部电容器板。

公开(公告)号：US07112480B2

公开(公告)日：2006-09-26

申请号：US11187472

申请日：2005-07-22

申请人： Shanjen Pan ,  James R. Todd ,  Sameer Pendharkar

发明人： Shanjen Pan ,  James R. Todd ,  Sameer Pendharkar

IPC分类号： H01L21/8238

CPC分类号： H01L29/7833 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0922

摘要： A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (70). A 20V, relatively high-power NMOS device (132) includes heavily doped P-type buried layers (76, 78) underneath the source (94) and drain regions (96) and spanning the gap between the P-well gate (90F) and adjacent P-well isolation regions (46, 50).

摘要翻译： CMOS集成电路（15A-B-C）包括同一芯片上的相对低功率（124,126）和大功率（132,134）CMOS晶体管。 20V，相对高功率的PMOS器件（134）包括重掺杂的N阱漏极区（70）。 20V，相对高功率的NMOS器件（132）包括在源极（94）和漏极区（96）下面的重掺杂的P型掩埋层（76,78），并跨越P阱栅极（90°F）之间的间隙 ）和相邻的P阱隔离区（46,50）。

公开(公告)号：US20060194401A1

公开(公告)日：2006-08-31

申请号：US11068117

申请日：2005-02-28

申请人： Binghua Hu ,  Sameer Pendharkar ,  Bill Wofford ,  Joseph Ramirez

发明人： Binghua Hu ,  Sameer Pendharkar ,  Bill Wofford ,  Joseph Ramirez

IPC分类号： H01L21/331 ,  H01L21/76

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/2652 ,  H01L21/823493 ,  H01L21/8249 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further include oxidizing the substrate using a wet oxidation process, the wet oxidation process and n-type dopant causing a ratio of oxidation of the implanted region to the unimplanted region to be 2:1 or greater, and then removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region.

摘要翻译： 本发明提供一种具有对准特征的半导体器件的制造方法。 除了其他步骤之外，制造半导体器件的方法可以包括将n型掺杂剂注入衬底中，从而在衬底中形成注入区域和未被注入的区域。 该方法可以进一步包括使用湿式氧化法，湿式氧化法和n型掺杂剂使注入区域与未被注入的区域的氧化比例为2:1或更大，然后除去氧化部分 从而在植入区域附近留下对准特征。

公开(公告)号：US20060186467A1

公开(公告)日：2006-08-24

申请号：US11063312

申请日：2005-02-21

申请人： Sameer Pendharkar ,  Jonathan Brodsky

发明人： Sameer Pendharkar ,  Jonathan Brodsky

IPC分类号： H01L29/76

CPC分类号： H01L29/66681 ,  H01L27/088 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/7816

摘要： A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.

摘要翻译： 半导体器件包括一个或多个LDMOS晶体管和一个更多的SCR-LDMOS晶体管。 每个LDMOS晶体管包括第一导电类型的LDMOS阱，在LDMOS阱中形成的第二导电类型的LDMOS源极区，以及由LDMOS阱的LDMOS漂移区分离的第二导电类型的LDMOS漏极区， 第二导电类型。 每个SCR-LDMOS晶体管包括第一导电类型的SCR-LDMOS阱，形成在SCR-LDMOS阱中的第二导电类型的SCR-LDMOS源区，第二导电类型的SCR-LDMOS漏极区和 SCR-LDMOS漏区和SCR-LDMOS漂移区之间的第一导电类型的阳极区。 阳极区域通过第二导电类型的SCR-LDMOS漂移区与SCR-LDMOS阱分离。

公开(公告)号：US20060051933A1

公开(公告)日：2006-03-09

申请号：US11198038

申请日：2005-08-05

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L21/76

CPC分类号： H01L29/0653 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/7835

摘要： A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions (32a, 32b, 32c) to break the channel region of the transistor into parallel sections. The gate electrode (35) extends over the multiple channel regions, and the underlying well (26) and thus the drift region (DFT) of the transistor extends along the full channel width. Channel stop doped regions (33) underlie the field oxide isolation structures (29c), and provide conductive paths for carriers during breakdown. Parasitic bipolar conduction, and damage due to that conduction, is therefore avoided.

摘要翻译： 公开了具有改进的击穿特性鲁棒性的漏极延伸金属氧化物半导体晶体管（40）。 场源氧化物隔离结构（29c）设置在源极区域（30）和漏极接触区域（32a，32b，32c）之间，以将晶体管的沟道区域断开成平行段。 栅极电极（35）在多个沟道区域上延伸，并且下面的阱（26）以及晶体管的漂移区域（DFT）沿整个沟道宽度延伸。 通道阻挡掺杂区域（33）位于场氧化物隔离结构（29c）的下面，并且在击穿期间为载体提供导电路径。 因此避免了寄生双极导电和由于导电导致的损坏。

公开(公告)号：US20060022278A1

公开(公告)日：2006-02-02

申请号：US11187472

申请日：2005-07-22

申请人： Shanjen Pan ,  James Todd ,  Sameer Pendharkar

发明人： Shanjen Pan ,  James Todd ,  Sameer Pendharkar

IPC分类号： H01L21/8238 ,  H01L29/94

CPC分类号： H01L29/7833 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0922

摘要： A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (70). A 20V, relatively high-power NMOS device (132) includes heavily doped P-type buried layers (76, 78) underneath the source (94) and drain regions (96) and spanning the gap between the P-well gate (90F) and adjacent P-well isolation regions (46, 50).

公开(公告)号：US20050253217A1

公开(公告)日：2005-11-17

申请号：US10832009

申请日：2004-04-26

申请人： Shanjen Pan ,  Sameer Pendharkar ,  James Todd

发明人： Shanjen Pan ,  Sameer Pendharkar ,  James Todd

IPC分类号： H01L21/8234 ,  H01L21/266 ,  H01L21/336 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/266 ,  H01L27/0623 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2029/42388

摘要： The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure (110) over the semiconductor substrate (105), the gate structure (110) having a gate corner (125). The transistor (100) also includes a drain-extended well (115) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The drain-extended well (115) also has a low-doped region (145) between high-doped regions (150), wherein an edge of the low-doped region (155) is substantially coincident with a perimeter (140) defined by the gate corner (125). Other embodiments of the present invention include a method of manufacturing a transistor (200) and an integrated circuit (300).

摘要翻译： 本发明在一个实施例中提供一种晶体管（100）。 晶体管（100）包括半导体衬底（105）上方的掺杂半导体衬底（105）和栅极结构（110），栅极结构（110）具有栅极拐角（125）。 晶体管（100）还包括由掺杂半导体衬底（105）围绕的漏极扩展阱（115）。 漏极扩展阱（115）具有与掺杂半导体衬底（105）相反的掺杂剂类型。 漏极扩展阱（115）还在高掺杂区域（150）之间具有低掺杂区域（145），其中低掺杂区域（155）的边缘基本上与由 门角（125）。 本发明的其他实施例包括制造晶体管（200）和集成电路（300）的方法。

公开(公告)号：US20050215018A1

公开(公告)日：2005-09-29

申请号：US11135544

申请日：2005-05-24

申请人： Pinghai Hao ,  Shanjen Pan ,  Sameer Pendharkar

发明人： Pinghai Hao ,  Shanjen Pan ,  Sameer Pendharkar

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/338 ,  H01L29/02 ,  H01L29/08 ,  H01L29/78 ,  H01L47/00

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

摘要： A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.

摘要翻译： 可以制造晶体管以显示减少的通道热载体效应。 根据本发明的一个方面，制造晶体管结构的方法包括将第一掺杂剂注入到轻掺杂漏极（LDD）区域中以在其中形成浅区域。 第一掺杂剂将衬底渗透至小于LDD结深度的深度。 将第二掺杂剂注入超过LDD结深度的衬底中以形成源/漏区。 第二掺杂剂的注入超过第一掺杂剂的大部分，以限定LDD区域中的浮动环，其缓和了通道热载流子效应。

公开(公告)号：US20050110081A1

公开(公告)日：2005-05-26

申请号：US10721567

申请日：2003-11-25

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0653 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/7835

摘要： A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions (32a, 32b, 32c) to break the channel region of the transistor into parallel sections. The gate electrode (35) extends over the multiple channel regions, and the underlying well (26) and thus the drift region (DFT) of the transistor extends along the full channel width. Channel stop doped regions (33) underlie the field oxide isolation structures (29c), and provide conductive paths for carriers during breakdown. Parasitic bipolar conduction, and damage due to that conduction, is therefore avoided.

摘要翻译： 公开了具有改善的击穿特性鲁棒性的漏极延伸金属氧化物半导体晶体管（40）。 场源氧化物隔离结构（29c）设置在源极区域（30）和漏极接触区域（32a，32b，32c）之间，以将晶体管的沟道区域断开成平行段。 栅极电极（35）在多个沟道区域上延伸，并且下面的阱（26）以及晶体管的漂移区域（DFT）沿整个沟道宽度延伸。 通道阻挡掺杂区域（33）位于场氧化物隔离结构（29c）的下面，并且在击穿期间为载体提供导电路径。 因此避免了寄生双极导电和由于导电导致的损坏。

公开(公告)号：US09806190B2

公开(公告)日：2017-10-31

申请号：US13282305

申请日：2011-10-26

申请人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

发明人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/12 ,  H01L29/10 ,  H01L29/861 ,  H01L27/06

CPC分类号： H01L29/7824 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/7818 ,  H01L29/7835 ,  H01L29/861

摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).