公开(公告)号：US20210005760A1

公开(公告)日：2021-01-07

申请号：US17023639

申请日：2020-09-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Binghua Hu ,  Alexei Sadovnikov ,  Abbas Ali ,  Yanbiao Pan ,  Stefan Herzer

IPC: H01L29/94 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.

公开(公告)号：US10593773B2

公开(公告)日：2020-03-17

申请号：US15720616

申请日：2017-09-29

Applicant: Texas Instruments Incorporated

Inventor： Umamaheswari Aghoram ,  Pushpa Mahalingam ,  Alexei Sadovnikov ,  Eugene C Davis

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/221 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/40 ,  H01L21/761 ,  H01L29/10

Abstract: A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure is formed between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon dioxide.

公开(公告)号：US20190019884A1

公开(公告)日：2019-01-17

申请号：US15999542

申请日：2018-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Doug Weiser ,  Mattias Erik Dahlstrom ,  Joel Martin Halbert

IPC: H01L29/66 ,  H01L29/808 ,  H01L29/10 ,  H01L21/265 ,  H01L23/535 ,  H01L21/324 ,  H01L29/06

CPC classification number: H01L29/66916 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/0692 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/808 ,  H01L29/8086

Abstract: A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.

公开(公告)号：US10079294B2

公开(公告)日：2018-09-18

申请号：US15195287

申请日：2016-06-28

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Doug Weiser ,  Mattias Erik Dahlstrom ,  Joel Martin Halbert

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/808

CPC classification number: H01L29/66916 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/0692 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/808 ,  H01L29/8086

Abstract: A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.

公开(公告)号：US20170373171A1

公开(公告)日：2017-12-28

申请号：US15195287

申请日：2016-06-28

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Doug Weiser ,  Mattias Erik Dahlstrom ,  Joel Martin Halbert

IPC: H01L29/66 ,  H01L23/535 ,  H01L21/324 ,  H01L29/808 ,  H01L21/265

CPC classification number: H01L29/66916 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/0692 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/808 ,  H01L29/8086

Abstract: A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.

公开(公告)号：US09773777B2

公开(公告)日：2017-09-26

申请号：US14991881

申请日：2016-01-08

Applicant: Texas Instruments Incorporated

Inventor： Andrew D Strachan ,  Alexei Sadovnikov ,  Gang Xue ,  Dening Wang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/6609 ,  H01L29/66113 ,  H01L29/861 ,  H01L29/8618

Abstract: A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm−3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.

公开(公告)号：US09633994B2

公开(公告)日：2017-04-25

申请号：US15050684

申请日：2016-02-23

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L27/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8249 ,  H01L29/423 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L27/0623 ,  H01L21/32139 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/423 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: A MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

公开(公告)号：US09595480B2

公开(公告)日：2017-03-14

申请号：US14561008

申请日：2014-12-04

Applicant: Texas Instruments Incorporated

Inventor： Natalia Lavrovskaya ,  Alexei Sadovnikov ,  Andrew D. Strachan

IPC: H01L21/337 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L27/06 ,  H01L21/8238

CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66106 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/866

Abstract: The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

Abstract translation: BiCMOS半导体结构中的双极型晶体管的beta通过用两种注入形成双极型晶体管的发射极来增加：在形成源极和漏极区域的同时形成第一发射极区域的源极 - 漏极注入，以及 在形成另一区域的同时形成第二发射极区域的附加注入。 附加植入物具有大于源极 - 漏极植入物的植入能量的植入能量。

公开(公告)号：US20160172245A1

公开(公告)日：2016-06-16

申请号：US15050808

申请日：2016-02-23

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L21/8249 ,  H01L29/49 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L27/0623 ,  H01L21/32139 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/423 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

Abstract translation: 一种以SiGe BICMOS技术制造MOSFET晶体管的方法，其结构在栅电极和漏极区之间形成漏极 - 栅极反馈电容屏蔽。 屏蔽不与栅极重叠，从而最小化对晶体管的输入电容的影响。 该过程不需要复杂或昂贵的处理，因为屏蔽由SiGe BICMOS技术中通常使用的双极母材组成。

公开(公告)号：US09306013B2

公开(公告)日：2016-04-05

申请号：US14286805

申请日：2014-05-23

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L27/0623 ,  H01L21/32139 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/423 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

Abstract translation: 一种以SiGe BICMOS技术制造MOSFET晶体管的方法，其结构在栅电极和漏极区之间形成漏极 - 栅极反馈电容屏蔽。 屏蔽不与栅极重叠，从而最小化对晶体管的输入电容的影响。 该过程不需要复杂或昂贵的处理，因为屏蔽由SiGe BICMOS技术中通常使用的双极母材组成。