公开(公告)号：US20210013111A1

公开(公告)日：2021-01-14

申请号：US16924937

申请日：2020-07-09

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Kandabara TAPILY ,  Lars LIEBMANN ,  Daniel CHANEMOUGAME ,  Mark GARDNER ,  H. Jim FULFORD ,  Anton J. DEVILLIERS

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423

Abstract: A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package.

公开(公告)号：US20250081551A1

公开(公告)日：2025-03-06

申请号：US18458630

申请日：2023-08-30

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and channel structures stacked over each other along a first direction substantially perpendicular to a working surface of the substrate and each configured to have a current direction along a second direction substantially parallel to the working surface of the substrate. Source/drain (S/D) structures are positioned on opposing sides of the channel structure along the second direction. Gate structures are positioned on opposite sides of the channel structures along a third direction substantially parallel to the working surface of the substrate. The channel structures each have a shape of a nanosheet extending substantially perpendicular to the working surface of the substrate.

公开(公告)号：US20250022756A1

公开(公告)日：2025-01-16

申请号：US18899835

申请日：2024-09-27

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHDYAY

IPC: H01L21/8238 ,  H01L21/822 ,  H01L27/092 ,  H01L29/78

Abstract: A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.

公开(公告)号：US20230301062A1

公开(公告)日：2023-09-21

申请号：US18075242

申请日：2022-12-05

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD ,  Partha MUKHOPADHYAY

IPC: H10B12/00 ,  H01L25/065 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/10805 ,  H01L27/10873 ,  H01L27/1085 ,  H01L25/0657 ,  H01L29/42392 ,  H01L29/0847 ,  H01L29/1033

Abstract: A semiconductor device includes a memory cell unit positioned over a substrate. The memory cell unit includes a transistor and a capacitor. The capacitor includes an inner conductor, a capacitor dielectric all around the inner conductor, an outer conductor all around the capacitor dielectric, and dielectric support structures below the inner conductor. The capacitor is elongated in a length direction parallel to a working surface of the substrate, and the dielectric support structures are spaced along the length direction. The transistor includes a channel structure, a gate structure all around the channel structure, and source/drain (S/D) regions on opposing ends of the channel structure.

公开(公告)号：US20230057139A1

公开(公告)日：2023-02-23

申请号：US17740691

申请日：2022-05-10

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L23/522 ,  H01L21/3105 ,  H01L21/762

Abstract: Aspects of the present disclosure provide a method for fabricating a semiconductor structure. For example, the method can include forming a stack of metal structures on a substrate, the stack of metal structures including multiple metal structures that are vertically stacked over and electrically separated from one another, each of the metal structures including a ring and one or more pad contacts extending from the ring, the rings of the metal structures being vertically aligned with one another. The method can also include forming one or more channel structures within the rings of the metal structures, the channel structures being electrically separated from one another and electrically separated from the substrate. The method can also include forming one or more interconnections that extend from a position above the stack of metal structures to corresponding one or more of the pad contacts of the metal structures.

公开(公告)号：US20220367289A1

公开(公告)日：2022-11-17

申请号：US17480380

申请日：2021-09-21

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L21/8234 ,  H01L21/822 ,  H01L21/768

Abstract: Aspects of the present disclosure provide a method for forming a semiconductor structure having separated vertical channel structures. The method can include forming a layer stack on a substrate, the layer stack including alternating metal layers and dielectric layers. The method can further include forming vertically stacked lower and upper vertical channel structures vertically extending through the layer stack, the lower and upper vertical channel structures being separated by a sacrificial layer. The method can further include forming source, drain and gate connections to the lower and upper vertical channel structures, the source, drain and gate connections extending horizontally from the lower and upper vertical channel structures and then vertically to a location above the upper vertical channel structure. The method can further include forming a vertical opening in the layer stack and removing the sacrificial layer through the vertical opening to separate the lower and upper vertical channel structures.

公开(公告)号：US20220359312A1

公开(公告)日：2022-11-10

申请号：US17453212

申请日：2021-11-02

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L21/8238 ,  H01L21/822 ,  H01L27/092 ,  H01L29/78

Abstract: A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.

公开(公告)号：US20220238328A1

公开(公告)日：2022-07-28

申请号：US17473248

申请日：2021-09-13

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS ,  Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/027 ,  H01L23/16

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. For example, the method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof. The method can further include attaching the first side of the first semiconductor structure to a carrier substrate. The method can further include forming a stress film on a second side of the first semiconductor structure. The method can further include separating the carrier substrate from the first semiconductor structure. The method can further include cutting the stress film and the first semiconductor structure to define at least one chiplet. The method can further include bonding the at least one chiplet to a second semiconductor structure having a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

公开(公告)号：US20220140112A1

公开(公告)日：2022-05-05

申请号：US17237609

申请日：2021-04-22

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER

IPC: H01L29/66 ,  H01L27/092 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/78

Abstract: Aspects of the present disclosure provide a method of fabricating a semiconductor device. For example, the method can include forming a multilayer stack on a substrate. The multilayer stack can include alternate metal layers and dielectric layers. The method can also include forming at least one opening through the multilayer stack to uncover the substrate and forming at least two vertical channel structures within the opening that are stacked on each other. The vertical channel structures can have source, gate and drain regions being in contact with the metal layers of the multilayer stack, respectively. The method can also include removing a central portion of the vertical channel structures and filling the central portion of the vertical channel structures with a dielectric core. The dielectric core can isolate the vertical channel structures from each other and from the substrate.

公开(公告)号：US20210351053A1

公开(公告)日：2021-11-11

申请号：US17381297

申请日：2021-07-21

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Anthony SCHEPIS ,  Anton J. DEVILLIERS

IPC: H01L21/67 ,  H01L23/544 ,  H01L21/027 ,  H01L23/528

Abstract: A method for marking a semiconductor substrate at the die level for providing unique authentication and serialization includes projecting a first pattern of actinic radiation onto a layer of photoresist on the substrate using mask-based photolithography, the first pattern defining semiconductor device structures and projecting a second pattern of actinic radiation onto the layer of photoresist using direct-write projection, the second pattern defining a unique wiring structure having a unique electrical signature.