公开(公告)号：US20060043475A1

公开(公告)日：2006-03-02

申请号：US11048295

申请日：2005-02-02

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/43

CPC分类号： H01L29/7395 ,  H01L27/0647 ,  H01L29/7393

摘要： A semiconductor device includes a P diffusion region formed in the surface of an N− epitaxial layer apart from other P diffusion regions; an N+ diffusion region formed in the surface of the P diffusion region so as to be surrounded by the P diffusion region; a second collector electrode provided on the N+ diffusion region and connected to a first collector electrode; and an electrode provided on and extending through the P diffusion region and the N− epitaxial layer to form a conducting path from the N− epitaxial layer to the P diffusion region. This semiconductor device can improve both the operation and the reverse conducting capability of an IGBT.

摘要翻译： 半导体器件包括形成在与其它P扩散区域相比的N +外延层的表面中的P扩散区域; 形成在P扩散区域的表面中的N + +扩散区域，以被P扩散区域包围; 设置在N + +扩散区上并连接到第一集电极的第二集电极; 以及设置在P扩散区和N +外延层上并延伸穿过P +外延层的电极，以形成从N +外延层到P扩散区的导电路径。 该半导体器件可以提高IGBT的工作和反向导通能力。

公开(公告)号：US20050212042A1

公开(公告)日：2005-09-29

申请号：US11134352

申请日：2005-05-23

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/861 ,  H01L29/868 ,  H01L27/10

CPC分类号： H01L29/0661 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/8611 ,  H01L29/868

摘要： A semiconductor layer (10) provided on a BOX (buried oxide) layer (2) includes a first P-type region (11), an N+-type region (12), and an N−-type region (13) which together form a diode. A plurality of second P-type regions (14) are provided on a bottom part of the semiconductor layer (10). A plurality of insulating oxide films (21) are interposed between the plurality of second P-type regions (14). When the diode is in a reverse-biased state, the second P-type region (14) directly below the N+-type region (12) is approximately the same in potential as the N+-type region (12). The second P-type region (14) will be lower in potential relative to this second P-type region (14) directly below the N+-type region (12), as the second P-type region (14) gets nearer to the first P-type region (11). Electric field concentration can thus be relaxed at an interface between the semiconductor layer (10) and the BOX layer (2), whereby improvement in breakdown voltage of the diode is realized.

摘要翻译： 设置在BOX（掩埋氧化物）层（2）上的半导体层（10）包括第一P型区域（11），N + +型区域（12）和N + 一起形成二极管的区域（13）。 多个第二P型区域（14）设置在半导体层（10）的底部。 在多个第二P型区域（14）之间插入有多个绝缘氧化膜（21）。 当二极管处于反向偏置状态时，N + / - 型区域（12）正下方的第二P型区域（14）的电位与N + +区域（12）。 作为第二P型区域，第二P型区域（14）的电位相对于N + +型区域（12）正下方的该第二P型区域（14） 区域（14）越接近第一P型区域（11）。 因此，可以在半导体层（10）和BOX层（2）之间的界面放宽电场浓度，从而实现二极管的击穿电压的提高。

公开(公告)号：US06878998B1

公开(公告)日：2005-04-12

申请号：US09661035

申请日：2000-09-13

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/76 ,  H01L29/78 ,  H01L23/58 ,  H01L27/082

CPC分类号： H01L29/7393 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/7809

摘要： N+-type diffusion regions, P-type diffusion region and others are formed at and near a surface of an N−-type epitaxial layer on a p-type silicon substrate. Gate electrode portions are formed on P-type diffusion region located between N−-type diffusion regions and N−-type epitaxial layer with a gate insulating film therebetween. A source electrode and a drain electrode are formed. Under a field isolating film, a P-type diffusion region is formed discretely in a direction crossing a direction of a current flow in the on state. Thereby, such a semiconductor device is obtained that rising of an on resistance can be suppressed in an on state while keeping an effect of reducing an electric field.

摘要翻译： N +型扩散区，P型扩散区等形成在p型硅衬底上的N +型外延层的表面附近。 栅电极部分形成在N型扩散区和N +型外延层之间的栅型绝缘膜之间的P型扩散区上。 形成源电极和漏电极。 在场隔离膜下，P型扩散区域在与导通状态下的电流方向交叉的方向上离散地形成。 从而，可以获得能够在保持降低电场效果的同时将导通电阻的上升抑制在导通状态的这种半导体装置。

公开(公告)号：US06642599B1

公开(公告)日：2003-11-04

申请号：US08689636

申请日：1996-08-13

申请人： Kiyoto Watabe ,  Tomohide Terashima

发明人： Kiyoto Watabe ,  Tomohide Terashima

IPC分类号： H01L2976

CPC分类号： H01L29/7835 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/7393

摘要： A high resistance n-type base layer is formed on a silicon substrate with an insulating layer made of a silicon oxide film therebetween. In the high resistance n-type base layer a p-ch MOS transistor is formed. The p-ch MOS transistor is electrically isolated from another element by trench isolation formed of a trench. A p+ source layer in the p-ch MOS transistor surrounds a periphery of a p+ drain layer and has, for example, an elliptical planar configuration. A semiconductor device thus formed has a high drive capacity and is suitable to high integration.

摘要翻译： 在硅衬底上形成有由其间的氧化硅膜构成的绝缘层的高电阻n型基极层。 在高电阻n型基极层中，形成p沟道MOS晶体管。 p沟道MOS晶体管通过由沟槽形成的沟槽隔离与另一元件电隔离。 p沟道MOS晶体管中的p +源极层围绕p +漏极层的周边，并且具有例如椭圆形平面构造。 这样形成的半导体器件具有高的驱动能力并且适合于高集成度。

公开(公告)号：US5624858A

公开(公告)日：1997-04-29

申请号：US576384

申请日：1995-12-21

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L21/8238 ,  H01L21/74 ,  H01L21/761 ,  H01L27/08 ,  H01L27/092 ,  H01L29/10 ,  H01L21/265

CPC分类号： H01L21/74 ,  H01L27/0927 ,  H01L29/1083

摘要： A low concentration impurity region 6 of a second conductivity type is formed to cover lower portion of a high concentration impurity region 8 of the second conductivity type. Consequently, impurity concentration gradient between the high concentration impurity region 8 of the second conductivity type and the low concentration impurity layer 2 of a first conductivity type can be made moderate to relax the electric field, which leads to provision of higher breakdown voltage of the semiconductor device. Further, the depth of impurity diffusion of the low concentration impurity region 6 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type is made at least three times the depth of impurity diffusion of the high concentration impurity region 8 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type. Therefore, minimum dimensions necessary for suppressing the electric field can be set in the semiconductor device, and therefore the semiconductor device comes to have higher breakdown voltage efficiently while not preventing miniaturization.

摘要翻译： 形成第二导电类型的低浓度杂质区6以覆盖第二导电类型的高浓度杂质区8的下部。 因此，可以使第二导电类型的高浓度杂质区域8和第一导电类型的低浓度杂质层2之间的杂质浓度梯度适度地放松电场，这导致提供半导体的更高的击穿电压 设备。 此外，第二导电类型的低浓度杂质区域6从第一导电类型的低浓度杂质层2的主表面的杂质扩散深度至少为高浓度杂质扩散深度的三倍 从第一导电类型的低浓度杂质层2的主表面的第二导电类型的杂质区8。 因此，可以在半导体器件中设定抑制电场所需的最小尺寸，因此半导体器件在不防止小型化的情况下有效地进行有效的高击穿电压。

公开(公告)号：US5495124A

公开(公告)日：1996-02-27

申请号：US141659

申请日：1993-10-26

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L21/8238 ,  H01L21/74 ,  H01L21/761 ,  H01L27/08 ,  H01L27/092 ,  H01L29/10 ,  H01L29/36

CPC分类号： H01L21/74 ,  H01L27/0927 ,  H01L29/1083

摘要： A low concentration impurity region 6 of a second conductivity type is formed to cover lower portion of a high concentration impurity region 8 of the second conductivity type. Consequently, impurity concentration gradient between the high concentration impurity region 8 of the second conductivity type and the low concentration impurity layer 2 of a first conductivity type can be made moderate to relax the electric field, which leads to provision of higher breakdown voltage of the semiconductor device. Further, the depth of impurity diffusion of the low concentration impurity region 6 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type is made at least three times the depth of impurity diffusion of the high concentration impurity region 8 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type. Therefore, minimum dimensions necessary for suppressing the electric field can be set in the semiconductor device, and therefore the semiconductor device comes to have higher breakdown voltage efficiently while not preventing miniaturization.

摘要翻译： 形成第二导电类型的低浓度杂质区6以覆盖第二导电类型的高浓度杂质区8的下部。 因此，可以使第二导电类型的高浓度杂质区域8和第一导电类型的低浓度杂质层2之间的杂质浓度梯度适度地放松电场，这导致提供半导体的更高的击穿电压 设备。 此外，第二导电类型的低浓度杂质区域6从第一导电类型的低浓度杂质层2的主表面的杂质扩散深度至少为高浓度杂质扩散深度的三倍 从第一导电类型的低浓度杂质层2的主表面的第二导电类型的杂质区8。 因此，可以在半导体器件中设定抑制电场所需的最小尺寸，因此半导体器件在不防止小型化的情况下有效地进行有效的高击穿电压。

公开(公告)号：US5289019A

公开(公告)日：1994-02-22

申请号：US889290

申请日：1992-05-28

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/336 ,  H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L29/66333 ,  H01L29/0834 ,  H01L29/7395 ,  H01L29/7396 ,  H01L2924/10158 ,  Y10S148/135 ,  Y10S438/977

摘要： There is disclosed an IGBT which includes an n.sup.+ layer (2A) , an n.sup.- layer (2B) , a p well region (3), an n.sup.+ diffusion region (4), a gate oxide film (5), a gate electrode (6) and an emitter electrode (8) around the upper major surface of a p.sup.+ substrate (1), similarly to conventional IGBTS. In the lower major surface of the p.sup.+ substrate (1) is formed an n.sup.+ diffusion region (10) which is adapted not to reach the n.sup.+ layer (2A) . The n.sup.+ diffusion region (10) and p.sup.+ substrate (1) are connected to a collector electrode (9) . When there is a small potential difference between the emitter and collector electrodes, holes are injected from the p.sup.+ substrate into the n.sup.- layer to provide a low ON-resistance. When the potential difference is large, a depletion layer extending from the n.sup.+ diffusion region is brought into a reach-through state to limit an increase in the amount of injected holes. This prevents the device from being broken down due to an excessively increased current density.

摘要翻译： 公开了一种IGBT，其包括n +层（2A），n层（2B），p阱区（3），n +扩散区（4），栅极氧化膜（5），栅电极（6） ）和围绕p +衬底（1）的上主表面的发射极（8），类似于常规IGBTS。 在p +基板（1）的下表面形成n +扩散区域（10），其适于不到达n +层（2A）。 n +扩散区（10）和p +衬底（1）连接到集电极（9）。 当发射极和集电极之间存在很小的电位差时，从p +衬底向n层注入空穴以提供低导通电阻。 当电位差大时，从n +扩散区延伸的耗尽层进入到达状态，以限制注入孔的量的增加。 这防止了由于电流密度过大而使器件分解。

公开(公告)号：US5155569A

公开(公告)日：1992-10-13

申请号：US735886

申请日：1991-07-25

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/74 ,  H01L21/332 ,  H01L29/745 ,  H01L29/749

CPC分类号： H01L29/66378 ,  H01L29/7455

摘要： A thyristor structure comprises a p.sup.+ -type substrate (21), an n-type base layer (22), a first p-type diffusion region (23) and an n.sup.+ -type diffusion region (25). A MOS structure comprises the base layer (22), first and second p-type diffusion regions (23, 24) and the n.sup.+ -type diffusion region (25). A positive voltage is applied to a gate electrode (27) to form a channel in a portion of the first diffusion region (23) just under the gate electrode (27), so that a cathode electrode (28) supplies carriers to the base layer (22) through the n.sup.+ -type diffusion region (25) and the channel, to turn on the thyristor. A negative voltage is applied to the gate electrode (27) to form a channel in a portion of the base layer (22) just under the gate electrode (27), so that the first p-type diffusion region (23) and the n.sup.+ -type diffusion region (25) are shorted through the channel, the second p-type diffusion region (24) and the cathode electrode (28), to turn off the thyristor.

公开(公告)号：US5091766A

公开(公告)日：1992-02-25

申请号：US573776

申请日：1990-08-28

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/744 ,  H01L21/332 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749

CPC分类号： H01L29/66378 ,  H01L29/7455

摘要： A thyristor of the present invention turns on by applying a specified voltage to a first control electrode and turns off by applying a specified voltage to a second control electrode. These first and second control electrodes are independent of each other, so that the turning-on and turning-off conditions can be determined independently. When a transistor having the second control electrode is turned on by applying the specified voltage to the second control electrode until just before the turning-on, a first main electrode and a first semiconductor region can be electrically connected, so that the back gate potential of the transistor having the first control electrode can be fixed at the potential of the first main electrode.

公开(公告)号：US4984063A

公开(公告)日：1991-01-08

申请号：US387762

申请日：1989-08-01

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L23/12 ,  H01L23/28 ,  H01L23/34 ,  H01L23/433 ,  H01L23/48 ,  H01L23/495 ,  H01L29/78

CPC分类号： H01L23/4334 ,  H01L23/49562 ,  H01L23/49579 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48096 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511

摘要： A semiconductor device chip holder which has a plurality of plates laminated together, each having a different thermal expansion coefficient. A semiconductor chip is mounted on the upper surface of the chip holder, and molding resin is disposed only on the upper side of the chip holder encapsulating the semiconductor chip. At high temperatures the bimetal effect due to this construction causes the chip holder to warp, which generates a stress acting on the semiconductor chip compressing it. The piezoresistance effect thus obtained reduces the on-resistance of the semiconductor chip, thereby enabling the device to exhibit a stable and low on-resistance over a wide temperature range.

摘要翻译： 一种半导体器件芯片保持器，其具有层压在一起的多个板，每个板具有不同的热膨胀系数。 半导体芯片安装在芯片保持器的上表面上，并且模塑树脂仅设置在封装半导体芯片的芯片保持器的上侧。 在高温下，由于这种结构引起的双金属效应导致芯片保持器翘曲，这产生作用在半导体芯片上的压力的压力。 由此得到的压阻效应降低了半导体芯片的导通电阻，从而使器件能够在宽温度范围内呈现稳定且低导通电阻。