公开(公告)号：US20080251838A1

公开(公告)日：2008-10-16

申请号：US12118159

申请日：2008-05-09

申请人： Syotaro Ono ,  Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Norio Yasuhara ,  Kenichi Matsushita ,  Shinichi Hodama ,  Akio Nakagawa

发明人： Syotaro Ono ,  Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Norio Yasuhara ,  Kenichi Matsushita ,  Shinichi Hodama ,  Akio Nakagawa

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7809

摘要： A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.

摘要翻译： 半导体器件包括：半导体衬底，至少其表面部分用作第一导电类型的低电阻漏极层; 连接到所述低电阻漏极层的第一主电极; 形成在低电阻漏极层上的第二导电类型的高电阻外延层; 选择性地形成在高电阻外延层上的第二导电型基极层; 选择性地形成在所述第二导电型基底层的表面部分中的第一导电型源极层; 在由所述第二导电型基底层夹持的区域中形成的沟槽，其深度从所述高电阻外延层的表面延伸到所述半导体衬底; 形成在沟槽的侧壁上的第一导电类型的jfet层; 形成在沟槽中的绝缘层; 形成在第二导电型基底层的表面部分中的第一导电类型的LDD层，以便围绕沟槽的顶面连接到第一导电型jfet层; 控制电极，其形成在所述半导体衬底上，以被分成多个部分，并形成在形成在所述LDD层的一部分表面上的栅极绝缘膜上，所述第一导电型源的端部 并且在由LDD层和第一导电型源极层夹在第二导电型基底层的表面的区域上， 以及与所述第一导电型源极层和所述第二导电型基极欧姆接触以便夹持所述控制电极的第二主电极。

公开(公告)号：US20080035992A1

公开(公告)日：2008-02-14

申请号：US11836383

申请日：2007-08-09

申请人： Yusuke KAWAGUCHI ,  Yoshihiro Yamaguchi ,  Syotaro Ono ,  Akio Nakagawa ,  Miwako Akiyama ,  Kazuya Nakayama ,  Masakazu Yamaguchi

发明人： Yusuke KAWAGUCHI ,  Yoshihiro Yamaguchi ,  Syotaro Ono ,  Akio Nakagawa ,  Miwako Akiyama ,  Kazuya Nakayama ,  Masakazu Yamaguchi

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/2815 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7828

摘要： This semiconductor device comprises a drift layer of a first conductivity type formed on a drain layer of a first conductivity type, and a drain electrode electrically connected to the drain layer. A semiconductor base layer of a second conductivity type is formed in a surface of the drift layer, and a source region of a first conductivity type is further formed in the semiconductor base layer.A source electrode is electrically connected to the source region and a semiconductor base layer. Plural gate electrodes are formed through a gate insulation film so that a semiconductor base layer may be sandwiched by the gate electrodes. The width of the semiconductor base layer sandwiched by the gate electrodes is 0.3 micrometers or less.

摘要翻译： 该半导体器件包括形成在第一导电类型的漏极层上的第一导电类型的漂移层和电连接到漏极层的漏电极。 在漂移层的表面上形成第二导电类型的半导体基底层，并且在半导体基底层中进一步形成第一导电类型的源极区。 源电极电连接到源区和半导体基层。 多个栅电极通过栅极绝缘膜形成，使得半导体基底层可以被栅电极夹持。 被栅电极夹持的半导体基底层的宽度为0.3微米以下。

公开(公告)号：US20070242223A1

公开(公告)日：2007-10-18

申请号：US10593881

申请日：2005-03-16

申请人： Akio Nakagawa

发明人： Akio Nakagawa

IPC分类号： A61B5/16

CPC分类号： A61B3/032 ,  A61B3/0008 ,  A61B3/112

摘要： It is an object of the present invention to provide a pupillary reflex checking apparatus that enables a subject to check his own pupillary reflex and that keeps down cost and to provide a fatigue recovery facilitating apparatus that includes the pupillary reflex checking apparatus. The pupillary reflex apparatus of the present invention includes, as essential elements of its structure, a reflecting unit and a stimulus applying unit. Of these, the reflecting unit has a structure which includes an optical reflecting surface disposed in a plane that intersects with a visual axis of a subject such that an image of a pupil of a subject's eye is formed on the optical reflecting surface. Further, the stimulus applying unit applies a stimulus to induce the pupillary reflex in the subject. Specifically, it is possible to use a light source which gives a light stimulus to the subject's eye, such as an LED light source, an electric bulb, a strobe, or the like, as the stimulus applying unit.

摘要翻译： 本发明的目的是提供一种瞳孔反射检查装置，其能够使对象检查自己的瞳孔反射并降低成本，并提供包括瞳孔反射检查装置的疲劳恢复促进装置。 本发明的瞳孔反射装置包括作为其结构的基本要素的反射单元和刺激施加单元。 其中，反射单元具有包括设置在与被摄体的视轴相交的平面中的光反射面的结构，使得在光反射面上形成被检眼的瞳孔图像。 此外，刺激施加单元施加刺激以诱导受试者中的瞳孔反射。 具体地说，作为刺激施加单元，可以使用给予对象眼睛的光刺激的光源，例如LED光源，电灯泡，闪光灯等。

公开(公告)号：US07230297B2

公开(公告)日：2007-06-12

申请号：US11127224

申请日：2005-05-12

申请人： Syotaro Ono ,  Akio Nakagawa ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

发明人： Syotaro Ono ,  Akio Nakagawa ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/1095

摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.

摘要翻译： 公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

公开(公告)号：US07227225B2

公开(公告)日：2007-06-05

申请号：US10829173

申请日：2004-04-22

申请人： Syotaro Ono ,  Yusuke Kawaguchi ,  Akio Nakagawa

发明人： Syotaro Ono ,  Yusuke Kawaguchi ,  Akio Nakagawa

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933

摘要： A second semiconductor region is formed on a first semiconductor region. A third semiconductor region is formed on a part of the second semiconductor region. A trench ranges from a surface of the third semiconductor region to the third semiconductor region and the second semiconductor region. The trench penetrates the third semiconductor region, and the depth of the trench is shorter than that of a deepest bottom portion of the second semiconductor region, and the second semiconductor region does not exist under a bottom surface of the trench. A gate insulating film is formed on facing side surfaces of the trench. First and second gate electrodes are formed on the gate insulating film. The first and second gate electrodes are separated from each other. The conductive material is formed between the first and second gate electrodes on the side surfaces of the trench, with an insulating film intervened therebetween.

摘要翻译： 在第一半导体区域上形成第二半导体区域。 在第二半导体区域的一部分上形成第三半导体区域。 沟槽的范围从第三半导体区域的表面到第三半导体区域和第二半导体区域。 沟槽穿透第三半导体区域，并且沟槽的深度比第二半导体区域的最深底部的深度短，并且第二半导体区域不存在于沟槽的底表面之下。 栅极绝缘膜形成在沟槽的相对的侧表面上。 在栅极绝缘膜上形成第一和第二栅电极。 第一和第二栅电极彼此分离。 导电材料形成在沟槽的侧表面上的第一和第二栅电极之间，绝缘膜介于其间。

公开(公告)号：US20070013351A1

公开(公告)日：2007-01-18

申请号：US11485466

申请日：2006-07-13

申请人： Toshiyuki Naka ,  Akio Nakagawa ,  Kazutoshi Nakamura

发明人： Toshiyuki Naka ,  Akio Nakagawa ,  Kazutoshi Nakamura

IPC分类号： G05F1/00

CPC分类号： H02M3/157 ,  H02M3/1588 ,  Y02B70/1466

摘要： An electronic power unit includes first and second MOS transistors and a digital control circuit. The first MOS transistor applies a voltage to the load. The second MOS transistor remains on while the first MOS transistor remains off and rectifies the current flowing in the load. The digital control circuit turns on the first transistor upon lapse of a first time interval from the time the second MOS transistor is turned off. The digital control circuit turns on the second MOS transistor upon lapse of a second time interval from the time the first MOS transistor is turned off. The digital control circuit controls the on-period of the first MOS transistor so that the voltage applied to the load is constant in a discontinuous conduction mode. The digital control circuit determines, while the voltage applied to the load is constant, an optimal value of the first time from the duty.

摘要翻译： 电子功率单元包括第一和第二MOS晶体管和数字控制电路。 第一个MOS晶体管向负载施加电压。 第二MOS晶体管保持导通，而第一MOS晶体管保持关断并且对负载中流动的电流进行整流。 数字控制电路在从第二MOS晶体管截止时起第一时间间隔开启第一晶体管。 数字控制电路在从第一MOS晶体管截止时经过第二时间间隔开启第二MOS晶体管。 数字控制电路控制第一MOS晶体管的导通周期，使得施加到负载的电压在不连续导通模式下是恒定的。 数字控制电路在施加到负载的电压是恒定的情况下确定第一次从占空比的最佳值。

公开(公告)号：US07026214B2

公开(公告)日：2006-04-11

申请号：US10957692

申请日：2004-10-05

申请人： Norio Yasuhara ,  Syotaro Ono ,  Kazutoshi Nakamura ,  Yusuke Kawaguchi ,  Shinichi Hodama ,  Akio Nakagawa

发明人： Norio Yasuhara ,  Syotaro Ono ,  Kazutoshi Nakamura ,  Yusuke Kawaguchi ,  Shinichi Hodama ,  Akio Nakagawa

IPC分类号： H01L21/00

CPC分类号： H01L29/402 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

公开(公告)号：US06705574B2

公开(公告)日：2004-03-16

申请号：US10238721

申请日：2002-09-11

申请人： Akio Nakagawa ,  Tetsuzo Nakazawa ,  Takashi Sato ,  Takaki Tsutsui

发明人： Akio Nakagawa ,  Tetsuzo Nakazawa ,  Takashi Sato ,  Takaki Tsutsui

IPC分类号： F16L300

CPC分类号： H01R13/5816

摘要： In a cable mounting structure, a casing body is formed with a through hole through which a cable is inserted. A first retainer is secured to a first part of the cable and fitted with the through hole. A second retainer is attached on the casing body while holding a second part of the cable. The first retainer is an elastic member having a groove fitted with an edge of the through hole. The second retainer includes a retaining member provided on the casing body while being formed with a guide groove, and a holding member detachably fitted into the guide groove.

摘要翻译： 在电缆安装结构中，壳体形成有电缆插入通孔。 第一保持器固定到电缆的第一部分并且装配有通孔。 在保持电缆的第二部分的同时，第二保持器附接在壳体上。 第一保持器是具有与通孔的边缘配合的槽的弹性构件。 第二保持器包括设置在壳体上的保持构件，同时形成有引导槽，并且保持构件可拆卸地装配到引导槽中。

公开(公告)号：US5780887A

公开(公告)日：1998-07-14

申请号：US261254

申请日：1994-06-14

申请人： Akio Nakagawa ,  Hiromichi Ohashi ,  Yoshihiro Yamaguchi ,  Kiminori Watanabe ,  Thuneo Thukakoshi

发明人： Akio Nakagawa ,  Hiromichi Ohashi ,  Yoshihiro Yamaguchi ,  Kiminori Watanabe ,  Thuneo Thukakoshi

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L29/1095 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/7393 ,  H01L29/7395

摘要： A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

公开(公告)号：US5689121A

公开(公告)日：1997-11-18

申请号：US480389

申请日：1995-06-07

申请人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

发明人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/745 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7455 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/0696 ,  H01L29/4236

摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

摘要翻译： 绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。