公开(公告)号：US08563961B2

公开(公告)日：2013-10-22

申请号：US13515435

申请日：2010-12-13

申请人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

发明人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

IPC分类号： H01L47/00

CPC分类号： H01L45/1666 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

摘要翻译： 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N> = 1）个第一栅极间绝缘层（11-15）和N个第一半导体 层（21p-24p）在基板的高度方向交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。

公开(公告)号：US08482961B2

公开(公告)日：2013-07-09

申请号：US13456195

申请日：2012-04-25

申请人： Satoru Hanzawa ,  Fumihiko Nitta ,  Nozomu Matsuzaki ,  Toshihiro Tanaka

发明人： Satoru Hanzawa ,  Fumihiko Nitta ,  Nozomu Matsuzaki ,  Toshihiro Tanaka

IPC分类号： G11C11/00

CPC分类号： G11C5/06 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144

摘要： In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

公开(公告)号：US08456940B2

公开(公告)日：2013-06-04

申请号：US13312620

申请日：2011-12-06

申请人： Satoru Hanzawa ,  Hitoshi Kume

发明人： Satoru Hanzawa ,  Hitoshi Kume

IPC分类号： G11C5/14 ,  G11C11/00

CPC分类号： G11C13/0023 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/72

摘要： A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

摘要翻译： 提供了具有高度可靠的操作的相变存储器。 半导体器件具有存储器阵列，其具有使用硫族化物材料和二极管层叠存储层的存储单元的结构，并且根据所选择的存储单元所在的层来改变初始化条件和写入条件。 初始化条件和写入条件（这里是复位条件）根据操作通过根据操作选择电流镜电路和通过电压选择电路和电流镜电路中的复位电流的控制机构而改变。

公开(公告)号：US20120248399A1

公开(公告)日：2012-10-04

申请号：US13515435

申请日：2010-12-13

申请人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

发明人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

IPC分类号： H01L27/24

CPC分类号： H01L45/1666 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

摘要翻译： 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。

公开(公告)号：US08169819B2

公开(公告)日：2012-05-01

申请号：US12688886

申请日：2010-01-17

申请人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

发明人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

IPC分类号： G11C11/00 ,  H01L29/80

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683

摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

公开(公告)号：US07907442B2

公开(公告)日：2011-03-15

申请号：US12445075

申请日：2006-10-12

申请人： Naoki Kitai ,  Satoru Hanzawa ,  Akira Kotabe

发明人： Naoki Kitai ,  Satoru Hanzawa ,  Akira Kotabe

IPC分类号： G11C11/00 ,  G11C7/10

CPC分类号： G11C11/419 ,  G11C7/065 ,  G11C13/0004 ,  G11C16/28 ,  G11C2013/0054 ,  G11C2213/82

摘要： In a readout circuit (RC) which detects a difference between a change that appears on a first signal line (CBL) and a change that appears on a second signal line (CBLdm) according to stored information of each selected memory cell, the first signal line and the second signal line are separated selectively from input nodes of a data latch circuit (DL) through second MOS transistors (MN3 and MN4) and capacitively coupled to the input nodes of the data latch circuit via gates of first MOS transistors (MP1 and MP2) respectively. In this separated state, the first and second signal lines and the input nodes of the data latch circuit are precharged to different voltages, so that the gate-to-source and drain-to-source voltages of the first MOS transistors are controlled by the voltages of the first and second signal lines respectively. Therefore, when the first and second signal lines are varied and the separated state is released upon a read operation, the first MOS transistors start to operate in a saturated region, thereby realizing a high-speed read operation.

摘要翻译： 在根据每个所选存储单元的存储信息检测出现在第一信号线（CBL）上的变化与出现在第二信号线（CBLdm）上的变化之间的差异的读出电路（RC）中，第一信号 线路和第二信号线通过第二MOS晶体管（MN3和MN4）选择性地从数据锁存电路（DL）的输入节点分离，并且经由第一MOS晶体管（MP1和...的栅极）电容耦合到数据锁存电路的输入节点 MP2）。 在这种分离状态下，数据锁存电路的第一和第二信号线和输入节点被预充电到不同的电压，使得第一MOS晶体管的栅极至源极和漏极到源极的电压由 分别是第一和第二信号线的电压。 因此，当第一和第二信号线变化并且在读取操作时释放分离状态时，第一MOS晶体管开始在饱和区域中工作，从而实现高速读取操作。

公开(公告)号：US07719870B2

公开(公告)日：2010-05-18

申请号：US11976532

申请日：2007-10-25

申请人： Satoru Hanzawa ,  Kiyoo Itoh ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Kiyoo Itoh ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Takeshi Sakata

IPC分类号： G11C7/00

CPC分类号： H01L27/101 ,  G11C7/12 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144

摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

摘要翻译： 本发明的目的是避免在由选择的字线上的所有存储单元中的选择晶体管导通的存储单元中构成的存储器阵列中的未选择的数据线被驱动，每个存储器单元使用依赖于可变电阻的存储元件和选择晶体管 。 为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。 由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。 因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。

公开(公告)号：US07341892B2

公开(公告)日：2008-03-11

申请号：US11368603

申请日：2006-03-07

申请人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

发明人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： H01L21/82

CPC分类号： H01L27/2454 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

公开(公告)号：US20080049481A1

公开(公告)日：2008-02-28

申请号：US11877310

申请日：2007-10-23

申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Kazuhiko Kajgaya

发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Kazuhiko Kajgaya

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C15/043

摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

摘要翻译： 有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。 本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。

公开(公告)号：US07116593B2

公开(公告)日：2006-10-03

申请号：US10485566

申请日：2002-09-13

申请人： Satoru Hanzawa ,  Kiyoo Itoh ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Kiyoo Itoh ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Takeshi Sakata

IPC分类号： G11C7/00

CPC分类号： H01L27/101 ,  G11C7/12 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144

摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

摘要翻译： 本发明的目的是避免在由存储单元组成的存储器阵列中驱动未选择的数据线，每个存储器单元在选择的字线上的所有存储单元中的选择晶体管时，根据可变电阻使用存储元件和选择晶体管 进行。 为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。 由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。 因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。