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    Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system
    43.
    发明授权
    Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system 失效
    用于确保多处理器系统中的多个高速缓冲存储器与主存储器之间的数据一致性的方案

    公开(公告)号：US5222224A

    公开(公告)日：1993-06-22

    申请号：US727296

    申请日：1991-07-09

    申请人： Michael E. Flynn ,  Scott Arnold ,  Stephen J. DeLaHunt ,  Tryggve Fossum ,  Ricky C. Hetherington ,  David J. Webb

    发明人： Michael E. Flynn ,  Scott Arnold ,  Stephen J. DeLaHunt ,  Tryggve Fossum ,  Ricky C. Hetherington ,  David J. Webb

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0822

    摘要： A method for insuring data consistency between a plurality of individual processor cache memories and the main memory in a multi-processor computer system is provided which is capable of (1) detecting when one of a set of predefined data inconsistency states occurs as a data transaction request is being processed, and (2) correcting the data inconsistency states so that the operation may be executed in a correct and consistent manner. In particular, the method is adapted to address two kinds of data inconsistency states: (1) A request for a operation from a system unit to main memory when the location to be written to is present in the cache of some processor unit-in such a case, data in the cache is "stale" and the data inconsistency is avoided by preventing the associated processor from using the "stale" data; and (2) when a read operation is requested of main memory by a system unit and the location to be read may be written or has already been written in the cache of some processor--in this case, the data in main memory is "stale" and the data inconsistency is avoided by insuring that the data returned to the requesting unit is the updated data in the cache. The presence of one of the above-described data inconsistency states is detected in a SCU-based multi-processing system by providing the SCU with means for maintaining a copy of the cache directories for each of the processor caches. The SCU continually compares address data accompanying memory access requests with what is stored in the SCU cache directories in order to determine the presence of predefined conditions indicative of data inconsistencies, and subsequently executes corresponding predefined fix-up sequences.

    摘要翻译： 提供了一种用于在多处理器计算机系统中确保多个单独处理器高速缓冲存储器与主存储器之间的数据一致性的方法，其能够（1）检测何时发生一组预定义数据不一致状态之一作为数据事务 正在处理请求，以及（2）校正数据不一致状态，以便以正确和一致的方式执行操作。 特别地，该方法适于解决两种数据不一致状态：（1）当要写入的位置存在于一些处理器单元的高速缓存中时，请求从系统单元到主存储器的操作 - 如此 一种情况下，缓存中的数据是“陈旧”的，并且通过防止相关联的处理器使用“过时”数据来避免数据不一致; 和（2）当通过系统单元请求主存储器的读取操作并且可以将待读取的位置写入或已经写入一些处理器的高速缓存中时 - 在这种情况下，主存储器中的数据是“过时的” “并且通过确保返回到请求单元的数据是高速缓存中的更新数据来避免数据不一致。 在基于SCU的多处理系统中检测到上述数据不一致状态之一的存在，通过为SCU提供用于维护每个处理器高速缓存的高速缓存目录的副本的装置。 SCU连续地将伴随存储器访问请求的地址数据与存储在SCU高速缓存目录中的内容进行比较，以便确定指示数据不一致性的预定义条件的存在，并且随后执行相应的预定义修补序列。

    DISTRIBUTED POWER MANAGEMENT FOR MULTI-CORE PROCESSORS
    45.
    发明申请
    DISTRIBUTED POWER MANAGEMENT FOR MULTI-CORE PROCESSORS 有权
    多核处理器的分布式电源管理

    公开(公告)号：US20140189413A1

    公开(公告)日：2014-07-03

    申请号：US13732289

    申请日：2012-12-31

    申请人： William C. Hasenplaugh ,  Tryggve Fossum

    发明人： William C. Hasenplaugh ,  Tryggve Fossum

    IPC分类号： G06F1/28

    CPC分类号： G06F1/3206 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3885 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/22

    摘要： A system and method for performing distributed power control in a processor comprising an array of cores enables each core to regulate power at least partially independently. Global power management settings are made accessible to all cores and communication between cores propagates power consumption information between nearest neighbors in the array. Each core attempts to best regulate its own power consumption in accordance with global power consumption information and/or specific instructions from a global power manager. In this manner local opportunistic load balancing may be achieved in a scalable manner suitable for a large array of cores.

    摘要翻译： 用于在包括核心阵列的处理器中执行分布式功率控制的系统和方法使得每个核心能够至少部分地独立地调节功率。 所有核心都可以访问全局电源管理设置，并且内核之间的通信会传播阵列中最近邻居之间的功耗信息。 每个核心都尝试根据全球功耗信息和/或来自全球电源管理员的特定指令来最佳地调节其自身的功耗。 以这种方式，可以以适合于大型核心阵列的可扩展方式来实现本地机会性负载平衡。

    Shared cache performance
    49.
    发明申请
    Shared cache performance 有权
    共享缓存性能

    公开(公告)号：US20070300016A1

    公开(公告)日：2007-12-27

    申请号：US11472877

    申请日：2006-06-21

    申请人： Tryggve Fossum

    发明人： Tryggve Fossum

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0864 ,  G06F12/084

    摘要： A method and apparatus for improving shared cache performance. In one embodiment, the present invention includes a cache having multiple ways. A locality tester measures a first locality of a first process and second locality of a second process. A first set of multiple ways stores the data used by the first process and a second set of multiple ways stores the data used by the second process, where the second set is a superset of the first set.

    摘要翻译： 一种用于提高共享缓存性能的方法和装置。 在一个实施例中，本发明包括具有多种方式的高速缓存。 地点测试者测量第一进程的第一地点和第二进程的第二地点。 第一组多路存储第一过程使用的数据，第二组多路存储由第二过程使用的数据，其中第二集合是第一集合的超集。

    Multicore processor having active and inactive execution cores
    50.
    发明申请
    Multicore processor having active and inactive execution cores 审中-公开
    具有活动和非活动执行核心的多核处理器

    公开(公告)号：US20060212677A1

    公开(公告)日：2006-09-21

    申请号：US11081306

    申请日：2005-03-15

    申请人： Tryggve Fossum

    发明人： Tryggve Fossum

    IPC分类号： G06F15/00

    CPC分类号： G06F9/5027 ,  G06F1/3203 ,  G06F1/3237 ,  G06F11/1629 ,  G06F11/2028 ,  G06F11/2043 ,  Y02D10/128

    摘要： Embodiments of a multicore processor having active and inactive execution cores are disclosed. In one embodiment, an apparatus includes a processor having a plurality of execution cores on a single integrated circuit, and a plurality of core identification registers. Each of the plurality of core identification registers corresponds to one of the execution cores to identify whether the execution core is active.

    摘要翻译： 公开了具有活动和非活动执行核心的多核处理器的实施例。 在一个实施例中，一种装置包括在单个集成电路上具有多个执行核心的处理器和多个核心识别寄存器。 多个核心识别寄存器中的每一个对应于一个执行核心，以识别执行核心是否是活动的。