利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

54 条记录 (耗时 0.022 秒)

    On-chip power supply noise detector
    41.
    发明授权
    On-chip power supply noise detector 失效
    片上电源噪声检测器

    公开(公告)号：US07355429B2

    公开(公告)日：2008-04-08

    申请号：US11089215

    申请日：2005-03-24

    申请人： Keith A. Jenkins ,  Anuja Sehgal ,  Peilin Song

    发明人： Keith A. Jenkins ,  Anuja Sehgal ,  Peilin Song

    IPC分类号： G01R31/02

    CPC分类号： G01R31/3004 ,  G01R19/16552

    摘要： Techniques for on-chip detection of integrated circuit power supply noise are disclosed. By way of example, a technique for monitoring a power supply line in an integrated circuit includes the following steps/operations. A first signal and a second signal are preconditioned. The first signal is representative of a voltage of the power supply line being monitored. The second signal is representative of a voltage of a reference power supply line. Preconditioning includes shifting respective levels of the voltages such that the voltages are within an output voltage range of comparator circuitry. Then, the preconditioned first signal and the preconditioned second signal are compared in accordance with the comparator circuitry. Comparison includes detecting when a difference exists between the voltage level of the preconditioned first signal and the voltage level of the preconditioned second signal.

    摘要翻译： 公开了片上检测集成电路电源噪声的技术。 作为示例，用于监视集成电路中的电源线的技术包括以下步骤/操作。 第一信号和第二信号被预处理。 第一信号代表被监测的电源线的电压。 第二信号代表参考电源线的电压。 预处理包括移动电压的各个电平，使得电压在比较器电路的输出电压范围内。 然后，根据比较器电路对预处理的第一信号和预处理的第二信号进行比较。 比较包括检测预处理的第一信号的电压电平与预处理的第二信号的电压电平之间的差异。

    Integrated CMOS spectrum analyzer for on-chip diagnostics using digital autocorrelation of coarsely quantized signals
    42.
    发明授权
    Integrated CMOS spectrum analyzer for on-chip diagnostics using digital autocorrelation of coarsely quantized signals 有权
    集成CMOS频谱分析仪，用于使用数字自相关粗量化信号进行片上诊断

    公开(公告)号：US07218091B1

    公开(公告)日：2007-05-15

    申请号：US11485390

    申请日：2006-07-13

    申请人： Keith A. Jenkins ,  Stanislav Polonsky

    发明人： Keith A. Jenkins ,  Stanislav Polonsky

    IPC分类号： G01R23/00

    CPC分类号： G01R23/16

    摘要： An integrated spectrum analyzer for performing on-chip power spectrum measurements, includes a digital autocorrelator that includes an analog input for inputting analog signal samples from a chip, an analog-to-digital converter for converting the analog signal samples into digital signal samples, a storage register for storing a first converted digital signal sample for a period of time, a digital multiplier for multiplying the first stored digital signal after the period of time with a second undelayed digital signal sample to produce a product of multiplication, and an accumulator for accumulating a plurality of products of multiplication for each new period of time. The digital autocorrelator computes an autocorrelation function based on the analog signal samples and is integrally formed on the chip for performing power spectrum measurements on the analog signal samples to compute the autocorrelation function.

    摘要翻译： 一种用于进行片上功率谱测量的集成频谱分析仪，包括数字自相关器，其包括用于输入来自芯片的模拟信号样本的模拟输入，用于将模拟信号样本转换成数字信号样本的模数转换器， 存储寄存器，用于存储一段时间内的第一转换数字信号采样;数字乘法器，用于将所述时间段之后的第一存储数字信号与第二未延迟数字信号采样相乘以产生乘法乘积;以及累加器，用于累加 多个产品的乘法每个新的时间段。 数字自相关器基于模拟信号样本计算自相关函数，并且一体形成在芯片上，用于对模拟信号采样进行功率谱测量，以计算自相关函数。

    On-Chip Delay Measurement Through a Transistor Array
    46.
    发明申请
    On-Chip Delay Measurement Through a Transistor Array 审中-公开
    通过晶体管阵列进行片上延迟测量

    公开(公告)号：US20130049791A1

    公开(公告)日：2013-02-28

    申请号：US13601122

    申请日：2012-08-31

    申请人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    发明人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    IPC分类号： G01R31/26

    CPC分类号： G11C29/023 ,  G01R31/31725 ,  G11C2029/5002

    摘要： A delay is measured through an array of transistors by selecting one transistor in the array; and applying a clock signal to the selected transistor. An output of the selected transistor is applied to a first input of a logic gate and a second clock signal based on the clock signal is applied to a second input of the logic gate. An output of the logic gate indicates a difference in arrival times of the signals at the two inputs. A clock signal can be applied to the selected transistor and a variable delay circuit. An output of the selected transistor is applied to a data input of a latch while an output of the variable delay circuit is applied to a clock input of the latch. The delay applied by the variable delay circuit is adjusted until a predefined transition is detected. The delay variation among the transistors can be obtained.

    摘要翻译： 通过选择阵列中的一个晶体管，通过晶体管阵列来测量延迟; 以及将时钟信号施加到所选择的晶体管。 所选择的晶体管的输出被施加到逻辑门的第一输入，并且基于时钟信号的第二时钟信号被施加到逻辑门的第二输入。 逻辑门的输出表示两个输入端的信号的到达时间差。 时钟信号可以施加到所选择的晶体管和可变延迟电路。 所选择的晶体管的输出被施加到锁存器的数据输入，而可变延迟电路的输出被施加到锁存器的时钟输入。 调整由可变延迟电路施加的延迟，直到检测到预定的转换。 可以获得晶体管之间的延迟变化。

    ON-CHIP MEASUREMENT OF AC VARIABILITY IN INDIVIDUAL TRANSISTOR DEVICES
    47.
    发明申请
    ON-CHIP MEASUREMENT OF AC VARIABILITY IN INDIVIDUAL TRANSISTOR DEVICES 有权

    公开(公告)号：US20120212238A1

    公开(公告)日：2012-08-23

    申请号：US13029214

    申请日：2011-02-17

    申请人： Karthik Balakrishnan ,  Keith A. Jenkins

    发明人： Karthik Balakrishnan ,  Keith A. Jenkins

    IPC分类号： G01R27/28

    CPC分类号： G01R31/2621 ,  G01R31/2882

    摘要： An apparatus for determining alternating current (AC) delay variation of a transistor device under test includes a ring oscillator, the ring oscillator having the transistor device under test configured within a feedback path of the ring oscillator; and circuitry configured to measure a difference between a first signal delay path and a second signal delay path, the first signal delay path being between a gate terminal and a drain terminal of the transistor device under test, and the second signal delay path being between a source terminal and the drain terminal of the transistor device under test.

    On chip temperature measuring and monitoring circuit and method
    48.
    发明授权
    On chip temperature measuring and monitoring circuit and method 有权
    片上温度测量和监测电路及方法

    公开(公告)号：US07780347B2

    公开(公告)日：2010-08-24

    申请号：US12177311

    申请日：2008-07-22

    申请人： Robert L. Franch ,  Keith A. Jenkins

    发明人： Robert L. Franch ,  Keith A. Jenkins

    IPC分类号： G01K7/01 ,  H01L17/78

    CPC分类号： H01L27/0251 ,  G01K7/01 ,  G01K7/015

    摘要： A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.

    摘要翻译： 一种器件温度测量电路，包括器件温度测量电路的集成电路（IC），表征器件温度的方法和监测温度的方法。 电路包括恒流源和夹紧装置。 钳位装置选择性地从恒流源分流电流，或允许电流流过PN结，其可以是场效应晶体管（FET）的主体到源极/漏极结。 电压测量直接来自PN结。 结温从测量的结电压确定。

    Electrical component tuned by conductive layer deletion
    49.
    发明授权
    Electrical component tuned by conductive layer deletion 失效
    通过导电层删除调整的电气元件

    公开(公告)号：US07538652B2

    公开(公告)日：2009-05-26

    申请号：US11512014

    申请日：2006-08-29

    申请人： Keith A. Jenkins ,  Mounir Meghelli

    发明人： Keith A. Jenkins ,  Mounir Meghelli

    IPC分类号： H01F5/00

    CPC分类号： H01F17/0013 ,  H01F21/12 ,  H01F41/045 ,  H01F2021/125 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/165 ,  H01L2924/00

    摘要： Techniques are disclosed for fabricating tunable electrical components in integrated circuits. For example, a method of tuning a value of an electrical component, such as a planar inductor, includes the steps of placing a conductive layer in proximity of the electrical component, and adjusting an amount of material that constitutes the conductive layer such that the value of the electrical component is tuned to a particular value. The adjustment step may be performed so as to select a frequency band with which the inductor is associated or to correct a manufacturing deviation in a frequency with which the inductor is associated.

    摘要翻译： 公开了用于在集成电路中制造可调电气部件的技术。 例如，调整诸如平面电感器的电气部件的值的方法包括以下步骤：将导电层放置在电气部件附近，并且调整构成导电层的材料的量，使得值 的电气元件被调谐到特定的值。 可以执行调整步骤以便选择与电感器相关联的频带或者校正与电感器相关联的频率中的制造偏差。

    On chip temperature measuring and monitoring circuit and method
    50.
    发明授权
    On chip temperature measuring and monitoring circuit and method 有权
    片上温度测量和监测电路及方法

    公开(公告)号：US07452128B2

    公开(公告)日：2008-11-18

    申请号：US11747620

    申请日：2007-05-11

    申请人： Robert L. Franch ,  Keith A. Jenkins

    发明人： Robert L. Franch ,  Keith A. Jenkins

    IPC分类号： G01K7/01 ,  H01L17/78

    CPC分类号： H01L27/0251 ,  G01K7/01 ,  G01K7/015

    摘要： A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.

    摘要翻译： 一种器件温度测量电路，包括器件温度测量电路的集成电路（IC），表征器件温度的方法和监测温度的方法。 电路包括恒流源和夹紧装置。 钳位装置选择性地从恒流源分流电流，或允许电流流过PN结，其可以是场效应晶体管（FET）的主体到源极/漏极结。 电压测量直接来自PN结。 结温从测量的结电压确定。