公开(公告)号：US20140332824A1

公开(公告)日：2014-11-13

申请号：US14340267

申请日：2014-07-24

Applicant: United Microelectronics Corp.

Inventor： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/16 ,  H01L29/10 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.

Abstract translation: 描述用于形成FinFET的半导体结构。 半导体结构包括半导体衬底，衬底上的FinFET的多个奇数鳍片，以及FinFET的奇数鳍片之间的衬底上的FinFET的多个偶数鳍片。 FinFET的奇数鳍从衬底定义。 FinFET的均匀鳍片与宽度和材料中的至少一个中的FinFET的奇数鳍不同，并且可以与FinFET的高度的奇数鳍不同。

公开(公告)号：US20130292775A1

公开(公告)日：2013-11-07

申请号：US13936214

申请日：2013-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Guang-Yaw Hwang ,  Ling-Chun Chou ,  I-Chang Wang ,  Shin-Chuan Huang ,  Jiunn-Hsiung Liao ,  Shin-Chi Chen ,  Pau-Chung Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chieh-Te Chen

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.

Abstract translation: 应变硅衬底结构包括设置在衬底上的第一晶体管和第二晶体管。 第一晶体管包括第一栅极结构和设置在第一栅极结构的两侧的两个第一源极/漏极区域。 第一源极/漏极到栅极间距在每个第一源极/漏极区域和第一栅极结构之间。 第二晶体管包括第二栅极结构和设置在第二栅极结构的两侧的两个源极/漏极掺杂区域。 第二源极/漏极到栅极间距在每个第二源极/漏极区域和第二栅极结构之间。 第一源极/漏极到栅极距离小于第二源极/漏极到栅极距离。

公开(公告)号：US20130256701A1

公开(公告)日：2013-10-03

申请号：US13905148

申请日：2013-05-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chan-Lon Yang ,  Ted Ming-Lang Guo ,  Chin-I Liao ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chun-Yuan Wu

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/6656 ,  H01L29/66636

Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.

Abstract translation: 应变硅沟道半导体结构包括具有上表面的衬底，形成在上表面上的栅极结构，在栅极结构的侧面处形成在衬底中的至少一个凹部，其中凹部具有至少一个侧壁，其具有 上侧壁和下侧壁在与栅极结构的方向上凹陷，并且上侧壁和水平面之间的夹角在54.5°-90°之间，并且填充到两个凹部中的外延层。

公开(公告)号：US09923095B2

公开(公告)日：2018-03-20

申请号：US15379486

申请日：2016-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

IPC: H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7853 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795

Abstract: The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

公开(公告)号：US09312180B2

公开(公告)日：2016-04-12

申请号：US14461444

申请日：2014-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien

IPC: H01L21/8242 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: Firstly, a substrate is provided, the substrate has a first region defined thereon, a plurality of fin structure is disposed within the first region, and an insulating layer is disposed on the substrate and between each fin structure; next, a first material layer is then formed on the insulating layer, and the fin structures is exposed simultaneously, afterwards, the fin structure is partially removed, and an epitaxial layer is then formed on the top surface of each remained fin structure.

Abstract translation: 本发明提供一种形成半导体结构的方法，包括以下步骤：首先，设置基板，其上限定有第一区域，在第一区域内设置多个翅片结构，绝缘层为 设置在基板上并在每个翅片结构之间; 接着，在绝缘层上形成第一材料层，同时对鳍片结构进行曝光，然后将翅片结构部分地去除，然后在每个残留的翅片结构的顶表面上形成外延层。

公开(公告)号：US09214551B2

公开(公告)日：2015-12-15

申请号：US14183545

申请日：2014-02-19

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Chang ,  Tien-Wei Yu ,  I-Cheng Hu ,  Chieh-Lung Wu ,  Yu-Shu Lin ,  Chun-Jen Chen ,  Tsung-Mu Yang ,  Tien-Chen Chan ,  Chin-Cheng Chien

IPC: H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.

Abstract translation: 描述了一种用于制造半导体器件的方法，以及用该方法制造的半导体器件。 在该方法中，在衬底中形成腔体，在高于65托的压力下进行第一外延工艺，以在空腔中形成缓冲层，并且进行第二外延工艺以在缓冲器上形成半导体化合物层 在空腔中的层。 在半导体装置中，空腔下侧的缓冲层的厚度S与空腔底部的缓冲层的厚度Y的比值（S / Y）为0.6〜0.8。

公开(公告)号：US20150303283A1

公开(公告)日：2015-10-22

申请号：US14279340

申请日：2014-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Ted Ming-Lang Guo

IPC: H01L29/66

CPC classification number: H01L29/66803 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes the following steps. A substrate including at least a fin layer and a plurality of gate electrodes is provided. A tilt and twist ion implantation is performed to form a plurality of doped regions in the fin layer. An etching process is performed to remove the doped regions to form a plurality of recesses in the fin layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供至少包括翅片层和多个栅电极的基板。 进行倾斜和扭转离子注入以在翅片层中形成多个掺杂区域。 执行蚀刻处理以去除掺杂区域以在散热片层中形成多个凹部。

公开(公告)号：US20150236158A1

公开(公告)日：2015-08-20

申请号：US14183545

申请日：2014-02-19

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Chang ,  Tien-Wei Yu ,  I-Cheng Hu ,  Chieh-Lung Wu ,  Yu-Shu Lin ,  Chun-Jen Chen ,  Tsung-Mu Yang ,  Tien-Chen Chan ,  Chin-Cheng Chien

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.

Abstract translation: 描述了一种用于制造半导体器件的方法，以及用该方法制造的半导体器件。 在该方法中，在衬底中形成腔体，在高于65托的压力下进行第一外延工艺，以在空腔中形成缓冲层，并且进行第二外延工艺以在缓冲器上形成半导体化合物层 在空腔中的层。 在半导体装置中，空腔下侧的缓冲层的厚度S与空腔底部的缓冲层的厚度Y的比值（S / Y）为0.6〜0.8。

公开(公告)号：US20140335674A1

公开(公告)日：2014-11-13

申请号：US13892424

申请日：2013-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-I Liao ,  Chin-Cheng Chien

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66636 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66795

Abstract: A manufacturing method of a semiconductor device is provided. The method includes at least the following steps. A gate structure is formed on a substrate. An epitaxial structure is formed on the substrate, wherein the epitaxial structure comprises SiGe, and the Ge concentration in the epitaxial structure is equal to or higher than 45%. A first cap layer is formed on the epitaxial structure, wherein the first cap layer comprises Si. The first cap layer is doped with boron for forming a flat top surface of the first cap layer.

Abstract translation: 提供一种半导体器件的制造方法。 该方法至少包括以下步骤。 在基板上形成栅极结构。 在衬底上形成外延结构，其中外延结构包括SiGe，外延结构中的Ge浓度等于或高于45％。 第一盖层形成在外延结构上，其中第一盖层包括Si。 第一盖层掺杂有硼以形成第一盖层的平坦顶表面。

公开(公告)号：US20140295629A1

公开(公告)日：2014-10-02

申请号：US13850887

申请日：2013-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Hsin-Kuo Hsu ,  Yu-Shu Lin ,  Szu-Hao Lai ,  Ming-Hua Chang

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  Y10S438/938

Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.

Abstract translation: 公开了一种形成半导体器件的方法。 至少一个栅极结构设置在衬底上，其中栅极结构包括形成在栅极的侧壁上的第一间隔物。 在覆盖栅极结构的衬底上沉积第一一次性间隔物层。 第一一次性间隔物材料层被蚀刻以在第一间隔物上形成第一一次性间隔物。 在覆盖栅极结构的衬底上沉积第二一次性间隔物材料层。 蚀刻第二一次性间隔材料层以在第一一次性间隔件上形成第二一次性间隔件。 通过使用第一和第二一次性间隔件作为掩模来去除衬底的一部分，以在栅极结构旁边的衬底中形成两个凹部。 在凹部中形成应力诱导层。