公开(公告)号：US11387408B2

公开(公告)日：2022-07-12

申请号：US17131767

申请日：2020-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Kun-Chen Ho ,  Yi-Syun Chou ,  Chang-Min Li ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  Jun Xie

IPC: H01L29/82 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

公开(公告)号：US11283007B2

公开(公告)日：2022-03-22

申请号：US17064614

申请日：2020-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Meng-Jun Wang ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming an etch stop layer on the first IMD layer; forming a second IMD layer on the etch stop layer; forming a patterned hard mask on the second IMD layer; performing a first etching process to form a contact hole in the second IMD layer for exposing the etch stop layer; performing a second etching process to remove the patterned hard mask; performing a third etching process to remove the etch stop layer and the first IMD layer for exposing the MTJ; and forming a metal interconnection in the contact hole.

公开(公告)号：US11121307B2

公开(公告)日：2021-09-14

申请号：US16575414

申请日：2019-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.

公开(公告)号：US20210119115A1

公开(公告)日：2021-04-22

申请号：US17134460

申请日：2020-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L43/08 ,  H01L21/768 ,  H01L43/02 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US20210057637A1

公开(公告)日：2021-02-25

申请号：US16575414

申请日：2019-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.

公开(公告)号：US20180061752A1

公开(公告)日：2018-03-01

申请号：US15271221

申请日：2016-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Huang ,  Ching-Li Yang ,  Yu-Cheng Tung ,  Yu-Tsung Lai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/53295 ,  H01L28/60

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a capacitor is formed on the substrate and a hard mask on the capacitor, in which the capacitor includes a bottom electrode, a capacitor dielectric layer, and a top electrode. Next, a protective layer is formed on the sidewalls of the top electrode and the bottom electrode, in which the protective layer includes metal oxide.

公开(公告)号：US09773860B1

公开(公告)日：2017-09-26

申请号：US15257930

申请日：2016-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Tsung Lai ,  Ching-Li Yang ,  Yu-Cheng Tung ,  Shih-Che Huang ,  Chih-Sheng Chang

IPC: H01L49/02

CPC classification number: H01L28/60

Abstract: A method for fabricating a capacitor is disclosed. First, a substrate is provided, a bottom electrode and a capacitor dielectric layer are formed on the substrate, a conductive layer is formed on the capacitor dielectric layer, a patterned hard mask is formed on the conductive layer, a patterned hard mask is used to remove part of the conductive layer to form a top electrode, the patterned hard mask is removed, and a protective layer is formed on a top surface and sidewalls of top electrode. Preferably, the protective layer includes metal oxides.

公开(公告)号：US08883648B1

公开(公告)日：2014-11-11

申请号：US14020948

申请日：2013-09-09

Applicant: United Microelectronics Corp.

Inventor： Ming-Da Hsieh ,  Yu-Tsung Lai ,  Hsuan-Hsu Chen

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/76802 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76879

Abstract: A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps: providing an underlying layer; forming a tri-layered photoresist on the underlying layer, which comprises forming a bottom photoresist layer on the underlying layer, forming a silicon-containing material layer on the bottom photoresist layer, and forming a patterned photoresist layer on the silicon-containing material layer; performing an atomic layer deposition (ALD) process for forming a thin layer on the tri-layered photoresist; and performing an etching process for forming a via hole, which comprises etching the silicon-containing material layer according to the thin layer on the tri-layered photoresist.

Abstract translation: 公开了一种半导体结构的制造方法。 该制造方法包括以下步骤：提供下层; 在下层上形成三层光致抗蚀剂，其包括在下层形成底部光致抗蚀剂层，在底部光致抗蚀剂层上形成含硅材料层，并在含硅材料层上形成图案化的光致抗蚀剂层; 执行在三层光致抗蚀剂上形成薄层的原子层沉积（ALD）工艺; 以及进行用于形成通孔的蚀刻工艺，其包括在三层光致抗蚀剂上根据薄层蚀刻含硅材料层。