公开(公告)号：US20160350022A1

公开(公告)日：2016-12-01

申请号：US15213350

申请日：2016-07-18

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  DINESH K. JAIN ,  STEPHAN GASKINS

IPC分类号： G06F3/06 ,  G11C17/16 ,  G06F12/0866

CPC分类号： G06F3/0631 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0866 ,  G06F12/12 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/283 ,  G06F2212/313 ,  G06F2212/601 ,  G06F2212/608 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C29/787 ,  G11C2029/4402

摘要： An apparatus includes a fuse array and a stores. The fuse array is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores. Each of the plurality of cores has sleep logic. The sleep logic is configured to subsequently access a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following a power gating event.

公开(公告)号：US20160336958A1

公开(公告)日：2016-11-17

申请号：US14882963

申请日：2015-10-14

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY

IPC分类号： H03M7/40 ,  G06F17/30

CPC分类号： H03M7/40 ,  G06F17/30339 ,  G06F17/30371

摘要： A hardware data compressor includes a first hardware engine that scans an input block of characters to produce a stream of tokens, the stream of tokens comprising replacement back pointers to matched strings of characters of the input block and non-replaced characters of the input block. The hardware data compressor also includes a second hardware engine that receives the stream of tokens and maintains a sorted list of symbols associated with the tokens. The hardware data compressor also includes the second hardware engine concurrently maintains the sorted list of symbols by frequency of occurrence as the first hardware engine produces the tokens of the stream.

摘要翻译： 硬件数据压缩器包括第一硬件引擎，其扫描输入的字符块以产生令牌流，令牌流包括将输入块的字符的匹配字符串和输入块的未替换字符替换回指针。 硬件数据压缩器还包括第二硬件引擎，其接收令牌流并且维护与令牌相关联的符号的排序列表。 硬件数据压缩器还包括第二硬件引擎，当第一硬件引擎产生流的令牌时，通过出现频率同时维护排序的符号列表。

公开(公告)号：US20160321192A1

公开(公告)日：2016-11-03

申请号：US15206524

申请日：2016-07-11

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  DINESH K. JAIN

IPC分类号： G06F12/128 ,  G11C17/18 ,  G06F12/0811 ,  G11C17/16

CPC分类号： G06F12/0875 ,  G06F1/24 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0638 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/44505 ,  G06F11/1008 ,  G06F11/1068 ,  G06F12/0646 ,  G06F12/0692 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/128 ,  G06F2212/1008 ,  G06F2212/1012 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/453 ,  G06F2212/601 ,  G06F2212/62 ,  G06F2212/69 ,  G11C17/16 ,  G11C17/18 ,  G11C29/52 ,  G11C29/802

摘要： An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.

摘要翻译： 一种装置包括半导体熔丝阵列，高速缓冲存储器和多个核。 半导体熔丝阵列设置在芯片上，其中编程了配置数据。 半导体熔丝阵列具有第一多个半导体熔丝，其被配置为存储压缩的高速缓存校正数据。 缓存存储器设置在管芯上。 多个芯设置在管芯上，其中多个芯中的每个芯耦合到半导体熔丝阵列和高速缓冲存储器，并且被配置为在上电/复位时访问半导体熔丝阵列，以解压缩压缩高速缓存 校正数据，并且分发解压缩的缓存校正数据以初始化高速缓冲存储器。

公开(公告)号：US20160170757A1

公开(公告)日：2016-06-16

申请号：US14950439

申请日：2015-11-24

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： GERARD M. COL ,  COLIN EDDY ,  G. GLENN HENRY

IPC分类号： G06F9/30 ,  G06F1/32

CPC分类号： G06F9/30083 ,  G06F1/3296 ,  G06F9/3834

摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a fuse array, configured to store the plurality of specified load instructions corresponding to the out-of-order processor which, upon initialization, accesses the fuse array to determine the plurality of specified load instructions.

摘要翻译： 一种包括第一和第二保留站的装置。 第一保留站调度负载微指令，并且在保持总线上指示负载微指令是否是指定的从指定资源（除了内核高速缓冲存储器）检索操作数的指定负载微指令。 第二保留站耦合到保持总线，并且在分配第一加载微指令之后的多个时钟周期之后，分派一个或多个取决于载入微指令以执行的较新的微指令，并且如果在 所述保持总线，所述加载微指令是指定的负载微指令，所述第二保留站被配置为停止所述一个或多个较小的微指令的分派，直到所述加载微指令已经检索到所述操作数。 多个非核心资源包括熔丝阵列，其被配置为存储对应于无序处理器的多个指定的加载指令，其在初始化时访问熔丝阵列以确定多个指定的加载指令。

公开(公告)号：US20150178196A1

公开(公告)日：2015-06-25

申请号：US14635113

申请日：2015-03-02

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  DINESH K. JAIN

IPC分类号： G06F12/06 ,  G06F12/08

CPC分类号： G06F12/0875 ,  G06F1/24 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0638 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/44505 ,  G06F11/1008 ,  G06F11/1068 ,  G06F12/0646 ,  G06F12/0692 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/128 ,  G06F2212/1008 ,  G06F2212/1012 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/453 ,  G06F2212/601 ,  G06F2212/62 ,  G06F2212/69 ,  G11C17/16 ,  G11C17/18 ,  G11C29/52 ,  G11C29/802

摘要： An apparatus is contemplated for storing and providing configuration data to an integrated circuit device, the apparatus has a fuse array and a plurality of cores. The fuse array is disposed on a die. The fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the fuse array. The each of the plurality of cores includes array control, configured to access the first and second pluralities of fuses, and configured to process first states of the first plurality of semiconductor fuses and second states of the second plurality of semiconductor fuses according to contents of a configuration data register.

公开(公告)号：US20180189640A1

公开(公告)日：2018-07-05

申请号：US15396571

申请日：2016-12-31

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  KIM C. HOUCK ,  PARVIZ PALANGPOUR

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06F12/0875 ,  G06F12/0862 ,  G06F9/30

CPC分类号： G06N3/063 ,  G06F9/3001 ,  G06F9/3893 ,  G06F12/0862 ,  G06F2212/6026 ,  G06N3/0445 ,  G06N3/0454

摘要： First/second memories hold rows of N weight/data words. Each of N processing units (PU) of index J have a register, an accumulator having an output, an arithmetic unit that performs an operation thereon to accumulate a result, the first input receives the output of the accumulator, the second input receives a respective first memory weight word, the third input receives a respective data word output by the register, and multiplexing logic receives a respective second memory data word and a data word output by the register of PU J−1 and outputs a selected data word to the register. PU J−1 for PU 0 is PU N−1. The multiplexing logic of PU 0 also receives the data word output by the register of PU (N/2)−1. The multiplexing logic of PU N/2 also receives the data word output by the register of PU N−1.

公开(公告)号：US20180189633A1

公开(公告)日：2018-07-05

申请号：US15396577

申请日：2016-12-31

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  KIM C. HOUCK ,  PARVIZ PALANGPOUR

IPC分类号： G06N3/04 ,  G06F9/38 ,  G06N3/063

摘要： First/second memories hold rows of N weight/data words. Each of N processing units (PU) of index J have a register, an accumulator having an output, an arithmetic unit that performs an operation thereon to accumulate a result, the first input receives the output of the accumulator, the second input receives a respective first memory weight word, the third input receives a respective data word output by the register, and multiplexing logic receives a respective second memory data word and a data word output by the register of PU J−1 and outputs a selected data word to the register. PU J−1 for PU 0 is PU N−1. The multiplexing logic of PU N/4 also receives the data word output by the register of PU (3N/4)−1. The multiplexing logic of PU 3N/4 also receives the data word output by the register of PU (N/4)−1.

公开(公告)号：US20170161067A1

公开(公告)日：2017-06-08

申请号：US15337140

申请日：2016-10-28

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  RODNEY E. HOOKER ,  TERRY PARKS ,  DOUGLAS R. REED

IPC分类号： G06F9/30 ,  G06F3/06 ,  G06F9/38

CPC分类号： G06F9/3016 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673 ,  G06F8/41 ,  G06F8/443 ,  G06F8/447 ,  G06F9/22 ,  G06F9/28 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/328 ,  G06F9/3836 ,  G06F9/3879 ,  G06F9/3897 ,  G06F15/7867 ,  G06F15/7871 ,  G06F15/7892

摘要： A processor with an expandable instruction set architecture for dynamically configuring execution resources. The processor includes a programmable execution unit (PEU) that may be programmed to perform a user-defined function in response to a user-defined instruction (UDI). The PEU includes programmable logic elements and programmable interconnectors that are collectively programmed to perform at least one processing operation. A UDI loader is responsive to a UDI load instruction that specifies a UDI and a location of programming information that is used to program the PEU. The PEU may be programmed for one or more UDIs for one or more processes. An instruction table stores each UDI and corresponding information to identify the UDI and possibly to reprogram the PEU if necessary. A UDI handler consults the instruction table to identify a received UDI and to send corresponding information to the PEU to execute the corresponding user-defined function.

公开(公告)号：US20170103321A1

公开(公告)日：2017-04-13

申请号：US15090696

申请日：2016-04-05

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  TERRY PARKS

IPC分类号： G06N3/08 ,  G06F9/30

CPC分类号： G06F15/82 ,  G06F1/10 ,  G06F7/483 ,  G06F7/49947 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/321 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3893 ,  G06F9/44505 ,  G06N3/04 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G06N3/088

摘要： A neural network unit including a register programmable with a representation of a reciprocal value of a divisor and a plurality of neural processing units (NPU). Each NPU has an ALU, an accumulator, and a reciprocal multiplier unit. The ALU performs arithmetic and logical operations on a sequence of operands to generate a sequence of results and accumulates the sequence of results as an accumulated value into the accumulator. The reciprocal multiplier unit receives the representation of the reciprocal value and the accumulated value and in response generates a result that is the quotient of the accumulated value and the divisor.

公开(公告)号：US20170103310A1

公开(公告)日：2017-04-13

申请号：US15090712

申请日：2016-04-05

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  TERRY PARKS

IPC分类号： G06N3/08 ,  G06N3/04

CPC分类号： G06F15/82 ,  G06F1/10 ,  G06F7/483 ,  G06F7/49947 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/321 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3893 ,  G06F9/44505 ,  G06N3/04 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G06N3/088

摘要： A neural network unit (NNU) includes N neural processing units (NPU). Each NPU has an arithmetic unit and an accumulator. First and second multiplexed registers of the N NPUs collectively selectively operate as respective first and second N-word rotaters. First and second memories respectively hold rows of N weight/data words and provide the N weight/data words of a row to corresponding ones of the N NPUs. The NPUs selectively perform: multiply-accumulate operations on rows of N weight words and on a row of N data words, using the second N-word rotater; convolution operations on rows of N weight words, using the first N-word rotater, and on rows of N data words, the rows of weight words being a data matrix, and the rows of data words being elements of a convolution kernel; and pooling operations on rows of N weight words, using the first N-word rotater.