公开(公告)号：US06316323B1

公开(公告)日：2001-11-13

申请号：US09532847

申请日：2000-03-21

申请人： Edberg Fang ,  Wen-Yi Hsieh ,  Teng-Chun Tsai

发明人： Edberg Fang ,  Wen-Yi Hsieh ,  Teng-Chun Tsai

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553

摘要： The proposed invention is used to prevent the bridging issue of salicide process and also to provide a self-aligned contacted process in conventional self-aligned silicide process. In short, the proposed invention is a two-step silicide process with a reverse spacer structure, and comprises following steps: providing a substrate; forming a pad layer on the substrate; forming a first cap layer on the pad layer; defining a trench region over the substrate and forming the trench; implanting first ions into part of the substrate that is uncovered by the first layer; forming a pair of spacers inside the trench; implanting second ions into part of the substrate that is not covered by the first layer and the spacers; forming a gate oxide layer that is located inside the trench; filling a polysilicon layer into the trench; capping a first metal layer on the polysilicon layer; performing a first rapid thermal process; removing unreacted the first metal layer; filling the trench by a second cap layer; removing the first cap layer and the pad layer that are not located inside the trench region, and then a gate structure is formed; forming a source and a drain inside the substrate; forming a second metal layer on the substrate; performing a second rapid thermal process; removing unreacted the second metal layer; performing a third rapid thermal process; forming a third cap layer on the substrate; and forming a pair of contacts inside the third cap layer.

摘要翻译： 所提出的发明用于防止自对准硅化物工艺的桥接问题，并且还提供了常规自对准硅化物工艺中的自对准接触工艺。 简而言之，本发明是具有反向间隔结构的两步硅化物工艺，包括以下步骤：提供衬底; 在衬底上形成衬垫层; 在所述垫层上形成第一盖层; 在衬底上限定沟槽区域并形成沟槽; 将第一离子注入未被第一层覆盖的部分基底; 在沟槽内形成一对垫片; 将第二离子注入未被第一层和间隔物覆盖的基底的一部分中; 形成位于沟槽内的栅氧化层; 将多晶硅层填充到沟槽中; 在多晶硅层上覆盖第一金属层; 执行第一快速热处理; 去除未反应的第一金属层; 通过第二盖层填充沟槽; 去除不位于沟槽区域内的第一覆盖层和焊盘层，然后形成栅极结构; 在衬底内形成源极和漏极; 在所述基板上形成第二金属层; 执行第二快速热处理; 去除未反应的第二金属层; 进行第三次快速热处理; 在所述基板上形成第三盖层; 以及在所述第三盖层内形成一对触点。

公开(公告)号：US06228709B1

公开(公告)日：2001-05-08

申请号：US09010684

申请日：1998-01-22

申请人： Wen-Yi Hsieh

发明人： Wen-Yi Hsieh

IPC分类号： H01L218242

CPC分类号： H01L28/84 ,  H01L21/31111 ,  H01L27/1085

摘要： A method of fabricating an HSG electrode. An electrode is defined before the formation of an HSG layer. The HSG layer is then formed on the top surface and the side wall of the electrode. The HSG layer is thermal oxidized in a furnace by rapid thermal process, and a silicon oxide layer is formed on the surface of the HSG layer. Dipping the electrode into a dilute solution of hydrogen fluoride or buffered oxide etching (BOE), the silicon oxide layer is lifted off while an HSG structure is remained on the top surface and the side wall of the electrode.

摘要翻译： 一种HSG电极的制造方法。 在形成HSG层之前定义电极。 然后在电极的顶表面和侧壁上形成HSG层。 HSG层通过快速热处理在炉中进行热氧化，并且在HSG层的表面上形成氧化硅层。 将电极浸入氟化氢或缓冲氧化物蚀刻（BOE）的稀释溶液中，氧化硅层被剥离，同时HSG结构保留在电极的顶表面和侧壁上。

公开(公告)号：US6022795A

公开(公告)日：2000-02-08

申请号：US73861

申请日：1998-05-07

申请人： Tung-Po Chen ,  Hong-Tsz Pan ,  Wen-Yi Hsieh

发明人： Tung-Po Chen ,  Hong-Tsz Pan ,  Wen-Yi Hsieh

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518

摘要： A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source/drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal. The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

公开(公告)号：US08926194B2

公开(公告)日：2015-01-06

申请号：US13014794

申请日：2011-01-27

申请人： Yen-Chih Chang ,  Wen-Yi Hsieh ,  Ke-Hao Chen

发明人： Yen-Chih Chang ,  Wen-Yi Hsieh ,  Ke-Hao Chen

IPC分类号： G02B6/36

CPC分类号： G02B6/36

摘要： An optical board (100) includes a base layer (1), an optical module (4) assembled to the base layer, and an optical layer (2) attached to the base layer and defining a receiving recess (23). The optical module includes a ferrule (41) received in the receiving recess and defining a number of grooves (4131), and a number of optical circuits (42) positioned in the grooves of the ferrule. The optical circuits extend outside of the ferrule and into the optical layer.

摘要翻译： 光学板（100）包括基底层（1），组装到基底层的光学模块（4）和安装在基底层上并限定接纳凹部（23）的光学层（2）。 光学模块包括容纳在容纳凹槽中并限定多个凹槽（4131）的套圈（41）和位于套圈凹槽中的多个光学电路（42）。 光学电路延伸到套圈的外部并进入光学层。

公开(公告)号：US08174904B2

公开(公告)日：2012-05-08

申请号：US12898691

申请日：2010-10-05

申请人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

发明人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/04 ,  G11C16/3445 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52

摘要： An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells.

摘要翻译： 本发明的一个实施例提供一种包括多个位线，多个存储单元和一个设备的存储器阵列。 多个存储单元中的每一个具有第一节点，第二节点和第三节点，其中第三节点耦合到多个位线之一。 该设备将多个位线耦合在一起以形成多个存储器单元之一的公共节点。

公开(公告)号：US07956631B2

公开(公告)日：2011-06-07

申请号：US12381420

申请日：2009-03-10

申请人： Ke-Hao Chen ,  Wen-Yi Hsieh

发明人： Ke-Hao Chen ,  Wen-Yi Hsieh

IPC分类号： G01R31/00

CPC分类号： G01R1/0466 ,  G01R1/07357

摘要： A test socket, adapted for connecting the semiconductor package and a printed circuit board comprises a base and a plurality of contacts received in the base. The base has a retaining board defining a plurality of first receiving holes and a positioning board defining a plurality of second receiving holes. The contacts has a contacting portion, an elastic portion and a retaining portion, the elastic portion is disposed between the retaining board and the positioning board and protruding rightward, and the contacting portion extends beyond the elastic portion and defines a acute angle with a horizontal line in a right hand before contacting with the semiconductor package to prevent the contacting portion from scratching with the left inner sidewall of the second receiving hole when pushed downward by the semiconductor package and rotating leftward.

公开(公告)号：US20080299810A1

公开(公告)日：2008-12-04

申请号：US12156288

申请日：2008-05-30

申请人： Wen-Yi Hsieh ,  Ke-Hao Chen

发明人： Wen-Yi Hsieh ,  Ke-Hao Chen

IPC分类号： H01R4/50

CPC分类号： G01R1/0466 ,  G01R31/2863

摘要： A burn-in socket for receiving an IC package includes a base, a platform located within the base for loading the IC package, a number of contacts arranged in the base for connecting with the IC package, a cover movably mounted upon the base, and at least one slider arrangement actuated by the cover. The slider arrangement comprises a first rod pivotally connected to the cover, a slider capable of abutting against the IC package, and a second rod with one end pivotally connected to the first rod and the other end pivotally connected to the slider.

摘要翻译： 用于接收IC封装的老化插座包括基座，位于基座内用于装载IC封装的平台，布置在基座中的与IC封装连接的多个触点，可移动地安装在基座上的盖子，以及 由盖驱动的至少一个滑动装置。 滑动装置包括一个可枢转地连接到该盖的第一杆，一个能够抵靠IC封装的滑块和一个第二杆，其一端可枢转地连接到第一杆，而另一端枢转地连接到滑块。

公开(公告)号：US20080293285A1

公开(公告)日：2008-11-27

申请号：US12154302

申请日：2008-05-22

申请人： Wen-Yi Hsieh

发明人： Wen-Yi Hsieh

IPC分类号： H01R13/62 ,  H01R12/00

CPC分类号： G01R1/0466 ,  G01R31/2863

摘要： An burn-in socket used for connecting an IC package includes an base, a actuated device floatably assembled on said base, a frame retained on said base, a plurality of contacts received in said base and a switch member rotatable assembled on said base. Said actuated device includes a plurality of sustaining shafts with a plurality of rollers ringed thereon. Said switch member includes a plurality of rotating shafts retained on said base and a plurality of latching members engaged with said rotating shafts and rotating between an open position and a locking position. Said rollers of sustaining shafts moveable engaged with said latching member, which lowers the abrasion while the latching members are rotating between said open position and said locking position around said rotating shafts.

摘要翻译： 用于连接IC封装的老化插座包括基座，可浮动地组装在所述基座上的致动装置，保持在所述基座上的框架，容纳在所述基座中的多个触点和可转动地组装在所述基座上的开关构件。 所述致动装置包括多个保持轴，多个辊环在其上。 所述开关构件包括保持在所述基座上的多个旋转轴和与所述旋转轴接合并在打开位置和锁定位置之间旋转的多个闩锁构件。 所述保持轴的所述辊可与所述闩锁构件可移动地接合，这降低了磨损，同时锁定构件在围绕所述旋转轴的所述打开位置和所述锁定位置之间旋转。

公开(公告)号：US20060109710A1

公开(公告)日：2006-05-25

申请号：US11273120

申请日：2005-11-14

申请人： Wen-Yi Hsieh ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Ken-Hui Chen

发明人： Wen-Yi Hsieh ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Ken-Hui Chen

IPC分类号： G11C16/06

CPC分类号： G11C16/0475 ,  G11C16/28 ,  G11C16/3454 ,  G11C16/3459

摘要： A program verification method for a memory device having a virtual array including a plurality of memory cells determines if leakage current passes through one or more neighboring memory cells to the programmed memory cell. The programmed memory cell is verified based on a first threshold state if leakage current is determined to pass through one or more neighboring memory cells. The programmed memory cell is verified based on a second threshold state if the leakage current is not determined to pass through one or more neighboring memory cells.

摘要翻译： 具有包括多个存储单元的虚拟阵列的存储器件的程序验证方法确定漏电流是否通过一个或多个相邻的存储器单元到编程的存储器单元。 如果确定泄漏电流通过一个或多个相邻存储器单元，则基于第一阈值状态来验证编程存储器单元。 如果泄漏电流未被确定通过一个或多个相邻存储器单元，则基于第二阈值状态来验证编程存储器单元。

公开(公告)号：US06403411B1

公开(公告)日：2002-06-11

申请号：US09208601

申请日：1998-12-08

申请人： Chih-Hsun Chu ,  Horng-Nan Chern ,  Kevin Lin ,  Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

发明人： Chih-Hsun Chu ,  Horng-Nan Chern ,  Kevin Lin ,  Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

IPC分类号： H01L218234

CPC分类号： H01L28/84 ,  H01L21/76895

摘要： A method for manufacturing the lower electrode of a DRAM capacitor. The method includes depositing polysilicon instead of amorphous silicon to form the lower electrode. Because polysilicon has a higher depositing temperature, it has a higher depositing rate capable of shortening depositing time. After forming the polysilicon lower electrode, the upper portion of the polysilicon layer is transformed into an amorphous layer by bombarding the polysilicon layer with ions to damage its internal structure. Eventually, hemispherical grain silicon is able to grow over the lower electrode, thereby increasing its surface area.

摘要翻译： 一种用于制造DRAM电容器的下电极的方法。 该方法包括沉积多晶硅而不是非晶硅以形成下电极。 由于多晶硅具有较高的沉积温度，因此具有更高的沉积速率，能够缩短沉积时间。 在形成多晶硅下电极之后，通过用离子轰击多晶硅层将多晶硅层的上部转变成非晶层，以破坏其内部结构。 最终，半球形晶粒硅能够在下电极上生长，从而增加其表面积。