公开(公告)号：US07782149B1

公开(公告)日：2010-08-24

申请号：US12355971

申请日：2009-01-19

申请人： William C. Athas

发明人： William C. Athas

IPC分类号： H03B11/04 ,  H03B11/10

CPC分类号： H03L7/099 ,  H03B5/1203 ,  H03B5/1212 ,  H03B5/1221 ,  H03B5/1228

摘要： A power source, a primary inductor, a load capacitance, and one or more tuned branch resonators and switching devices are coupled to generate pulses which represent a superposition of sinusoidal waveforms. The primary inductor is connected between the power source and the load. At the start of each cycle the load is coupled to ground and each tuned-branch resonators is reinitialized to re-energize the circuits and to stabilize the waveform when the frequencies of the sinusoidal waveforms are non-periodic.

摘要翻译： 电源，初级电感器，负载电容以及一个或多个调谐分支谐振器和开关器件被耦合以产生表示正弦波形叠加的脉冲。 主电感连接在电源和负载之间。 在每个周期的开始，负载被耦合到地，并且每个调谐支路谐振器被重新初始化以重新激励电路，并且当正弦波形的频率是非周期性时稳定波形。

公开(公告)号：US07681013B1

公开(公告)日：2010-03-16

申请号：US10038473

申请日：2001-12-31

申请人： Sushma Shrikant Trivedi ,  Jack Benkual ,  Joseph P. Bratt ,  William C. Athas

发明人： Sushma Shrikant Trivedi ,  Jack Benkual ,  Joseph P. Bratt ,  William C. Athas

IPC分类号： G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/30014 ,  G06F9/30047 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30141 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3885 ,  G06F9/3895

摘要： Methods and apparatuses for variable length decoding using multiple look-up tables simultaneously. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a string of bits; generating a plurality of indices using a plurality of segments of bits in the string of bits; looking up simultaneously a plurality of entries from a plurality of look-up tables using the plurality of indices; and combining the plurality of entries into a first result. The above operations are performed in response to the microprocessor receiving the single instruction.

摘要翻译： 同时使用多个查找表进行可变长度解码的方法和装置。 在本发明的一个方面，微处理器响应于接收单个指令而执行的方法包括：接收一串比特; 使用所述比特串中的多个比特段来生成多个索引; 使用多个索引从多个查找表中同时查找多个条目; 以及将所述多个条目组合成第一结果。 响应于微处理器接收到单个指令执行上述操作。

公开(公告)号：US20090259420A1

公开(公告)日：2009-10-15

申请号：US12242700

申请日：2008-09-30

申请人： Thomas C. Greening ,  P. Jeffrey Ungar ,  William C. Athas

发明人： Thomas C. Greening ,  P. Jeffrey Ungar ,  William C. Athas

IPC分类号： G01R31/36 ,  H02J7/04 ,  H01M6/00

CPC分类号： H02J7/0072 ,  H01M4/364 ,  H01M4/525 ,  H01M4/5815 ,  H01M4/5825 ,  H01M4/587 ,  H01M10/0525 ,  H01M10/0566 ,  H01M10/44 ,  Y02E60/122 ,  Y02T10/7011

摘要： Some embodiments of the present invention provide a system that adaptively charges a battery, wherein the battery is a lithium-ion battery which includes a transport-limiting electrode, an electrolyte separator and a non-transport-limiting electrode. To charge the battery, the system first determines a lithium surface concentration at an interface between the transport-limiting electrode and the electrolyte separator. Next, the system uses the determined lithium surface concentration to control a charging process for the battery so that the charging process maintains the lithium surface concentration within set limits.

摘要翻译： 本发明的一些实施例提供了一种对电池进行自适应充电的系统，其中电池是锂离子电池，其包括传输限制电极，电解质分离器和非传输限制电极。 为了对电池充电，系统首先确定在传输限制电极和电解质分离器之间的界面处的锂表面浓度。 接下来，系统使用确定的锂表面浓度来控制电池的充电过程，使得充电过程将锂表面浓度保持在设定的限度内。

公开(公告)号：US20090138745A1

公开(公告)日：2009-05-28

申请号：US11986892

申请日：2007-11-26

申请人： John Gregory Dorsey ,  William C. Athas

发明人： John Gregory Dorsey ,  William C. Athas

IPC分类号： G06F1/08

CPC分类号： H04B15/04 ,  H04B15/02

摘要： Electronic devices such as portable electronic devices contain electronic components. The electronic components may include radio-frequency transceiver circuitry. The radio-frequency transceiver circuitry may be used for handling data communications and cellular telephone voice communications. One or more adjustable clock sources may be provided within the electronic device. The adjustable clock sources may be based on phase-locked-loop circuits. A clock manager may determine which frequencies are being used by the radio-frequency transceiver circuitry and other components in the electronic device. The clock manager may use this information to compute a list of safe fundamental clock signal frequencies. Based on the list of safe clock signal frequencies, the clock manager may dynamically adjust the clock sources to avoid collisions between harmonics of the clock signals from the clock sources and the frequencies used by the transceiver circuitry and other components.

摘要翻译： 电子设备如便携式电子设备包含电子元件。 电子部件可以包括射频收发器电路。 射频收发器电路可以用于处理数据通信和蜂窝电话语音通信。 可以在电子设备内提供一个或多个可调时钟源。 可调时钟源可以基于锁相环电路。 时钟管理器可以确定射频收发器电路和电子设备中的其他组件正在使用哪些频率。 时钟管理器可以使用该信息来计算安全基本时钟信号频率的列表。 基于安全时钟信号频率的列表，时钟管理器可以动态地调整时钟源，以避免来自时钟源的时钟信号的谐波与收发器电路和其他组件使用的频率之间的冲突。

公开(公告)号：US07504852B2

公开(公告)日：2009-03-17

申请号：US11673934

申请日：2007-02-12

申请人： Lars G. Svensson ,  William C. Athas

发明人： Lars G. Svensson ,  William C. Athas

IPC分类号： H03K19/003

CPC分类号： H04L25/028 ,  H03K3/00 ,  H03K17/00 ,  H03K19/0005 ,  H03K19/0019 ,  H04L25/0278 ,  H04L25/0286 ,  H04L25/0298

摘要： A system and method for reducing reflections in a transmission line and for recovering energy from the load in the transmission during the process. At least three drive signal levels are utilized. The transition from the second level to the third level during a rising transition and the transition from the second level to the first level during a falling transition is timed to coincide with the arrival of the reflected signal from the immediately-preceding transition. A capacitor is advantageously used as the source for the intermediate drive signal levels and advantageously facilitates energy recovery and conservation.

摘要翻译： 一种用于减少传输线中的反射并且在该过程期间从传输中的负载中恢复能量的系统和方法。 至少使用三个驱动信号电平。 在上升过渡期间，从第二级到第三级的转变以及在下降的转换期间从第二级到第一级的转变被定时与来自紧接在前的转换的反射信号的到达相一致。 有利地，电容器用作中间驱动信号电平的源，并且有利地有助于能量回收和保存。

公开(公告)号：US07340622B2

公开(公告)日：2008-03-04

申请号：US11591866

申请日：2006-11-01

申请人： Keith A. Cox ,  William C. Athas

发明人： Keith A. Cox ,  William C. Athas

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y10T307/735 ,  Y10T307/852

摘要： One embodiment of the present invention provides a system that facilitates selectively increasing the operating frequency of an electronic circuit, such as a computer system. The system begins by operating in a low-power state with the frequency and voltage of the electronic circuit set to low levels. Upon recognizing the need for performance beyond the low power level, the electronic circuit enters the first-intermediate power state. In this first-intermediate power state, the frequency and voltage are set to first-intermediate levels. Upon recognizing the need for performance beyond the first-intermediate power state, the electronic circuit enters the maximum-sustainable power state. In this power state, the frequency and voltage are set to maximum sustainable levels. Upon recognizing the need for performance beyond the maximum-sustainable power state, the electronic circuit temporarily enters a boosted power state beyond the maximum-sustainable power state. In this boosted power state, the frequency and voltages are set to levels beyond the maximum sustainable levels.

摘要翻译： 本发明的一个实施例提供一种有助于选择性地增加诸如计算机系统的电子电路的操作频率的系统。 该系统以低功率状态运行，电子电路的频率和电压设置为低电平。 当识别出超出低功率电平的性能需要时，电子电路进入第一中间功率状态。 在该第一中间功率状态下，将频率和电压设置为第一中间电平。 当认识到超过第一中间功率状态的性能需要时，电子电路进入最大可持续功率状态。 在这种电源状态下，频率和电压被设置为最大可持续水平。 当认识到超出最大可持续功率状态的性能需求时，电子电路暂时进入超出最大可持续功率状态的升压功率状态。 在这种提升功率状态下，频率和电压被设置为超出最大可持续水平的水平。

公开(公告)号：US07171570B2

公开(公告)日：2007-01-30

申请号：US10838310

申请日：2004-05-03

申请人： Keith A. Cox ,  William C. Athas

发明人： Keith A. Cox ,  William C. Athas

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y10T307/735 ,  Y10T307/852

摘要： One embodiment of the present invention provides a system that facilitates selectively increasing the operating frequency of an electronic circuit, such as a computer system. The system begins by operating in a low-power state with the frequency and voltage of the electronic circuit set to low levels. Upon recognizing the need for performance beyond the low power level, the electronic circuit enters the first-intermediate power state. In this first-intermediate power state, the frequency and voltage are set to first-intermediate levels. Upon recognizing the need for performance beyond the first-intermediate power state, the electronic circuit enters the maximum-sustainable power state. In this power state, the frequency and voltage are set to maximum sustainable levels. Upon recognizing the need for performance beyond the maximum-sustainable power state, the electronic circuit temporarily enters a boosted power state beyond the maximum-sustainable power state. In this boosted power state, the frequency and voltages are set to levels beyond the maximum sustainable levels.

摘要翻译： 本发明的一个实施例提供一种有助于选择性地增加诸如计算机系统的电子电路的操作频率的系统。 该系统以低功率状态运行，电子电路的频率和电压设置为低电平。 当识别出超出低功率电平的性能需要时，电子电路进入第一中间功率状态。 在该第一中间功率状态下，将频率和电压设置为第一中间电平。 当认识到超过第一中间功率状态的性能需要时，电子电路进入最大可持续功率状态。 在这种电源状态下，频率和电压被设置为最大可持续水平。 当认识到超出最大可持续功率状态的性能需求时，电子电路暂时进入超出最大可持续功率状态的升压功率状态。 在这种提升功率状态下，频率和电压被设置为超出最大可持续水平的水平。

公开(公告)号：US07005893B1

公开(公告)日：2006-02-28

申请号：US10031672

申请日：2000-07-18

申请人： William C. Athas ,  Nestor Tzartzanis ,  Weihua Mao ,  Lena Peterson

发明人： William C. Athas ,  Nestor Tzartzanis ,  Weihua Mao ,  Lena Peterson

IPC分类号： H03K19/096

CPC分类号： H03K19/0019

摘要： High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer (101) is used to drive the signal line. The receiving end of the line is connected to a jam latch (123), preferably followed by an n-latch (125), followed by the digital logic (109), and followed by a second n-latch (127). The first n-latch is eliminated in an alternative embodiment, preferably one that uses complementary data signals.

摘要翻译： 高性能时钟供电逻辑运行在低于​​电源电平，并减少对更快数字逻辑电路的需求。 在优选实施例中，使用时钟缓冲器（101）来驱动信号线。 线的接收端连接到卡锁闩锁（123），优选地跟随着n锁存器（125），随后是数字逻辑（109），随后是第二n锁存器（127）。 在替代实施例中，优选地使用互补数据信号的第一个n锁存器被消除。

公开(公告)号：US06966008B2

公开(公告)日：2005-11-15

申请号：US10975520

申请日：2004-10-27

申请人： William C. Athas

发明人： William C. Athas

IPC分类号： G06F1/20 ,  G06F1/32 ,  G06F1/04 ,  G06F1/08

CPC分类号： G06F1/206 ,  G06F1/3203 ,  Y02D10/126

摘要： One embodiment of the present invention provides a system that facilitates temporarily increasing the operating frequency of an electronic circuit, such as a computer system, beyond a maximum sustainable operating frequency. Upon receiving a request to operate at a higher frequency, the system determines the thermal energy level of a cooling system for the circuit. If the thermal energy level is below a threshold level for the thermal capacity of the cooling system, the system increases the operating frequency of the circuit to a frequency that is greater than the maximum sustainable operating frequency for a period of limited duration. This period of limited duration is short enough to ensure that a temperature increase, caused by increasing the operating frequency, does not raise the operating temperature of the circuit above a maximum operating temperature.

公开(公告)号：US06867631B1

公开(公告)日：2005-03-15

申请号：US10418622

申请日：2003-04-18

申请人： William C. Athas ,  Keith A. Cox

发明人： William C. Athas ,  Keith A. Cox

IPC分类号： H03K3/00 ,  H03K5/04 ,  H03K5/135 ,  H03K5/1534

CPC分类号： H03K5/135 ,  H03K5/04 ,  H03K5/1534

摘要： Methods and apparatuses for generating a synchronous digital output signal stream from two digital input signal streams. In one aspect of the present invention, a method to generate a digital output signal stream from two digital input signal streams includes: detecting a first transition edge in a first digital input signal stream; and generating a third transition edge in a digital output signal stream. The third transition edge corresponds to the first transition edge; and the third transition edge is synchronized substantially with a second transition edge in a second digital input signal stream. In one example according to this aspect, a third digital signal stream is generated from synchronizing substantially transition edges of the first digital input signal stream with transition edges of the second digital input signal streams; and the first transition edge is detected using the third digital signal stream (e.g., comparing the third digital signal stream with a delayed version of the third digital signal stream).

摘要翻译： 用于从两个数字输入信号流产生同步数字输出信号流的方法和装置。 在本发明的一个方面，一种从两个数字输入信号流产生数字输出信号流的方法包括：检测第一数字输入信号流中的第一过渡沿; 以及在数字输出信号流中产生第三过渡沿。 第三过渡边缘对应于第一过渡边缘; 并且第三过渡边缘基本上与第二数字输入信号流中的第二过渡边沿同步。 在根据该方面的一个示例中，通过使第一数字输入信号流的大部分过渡边沿与第二数字输入信号流的过渡边沿同步来产生第三数字信号流; 并且使用第三数字信号流（例如，将第三数字信号流与第三数字信号流的延迟版本进行比较）来检测第一过渡沿。