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公开(公告)号：US20170170394A1
公开(公告)日：2017-06-15
申请号：US14967386
申请日：2015-12-14
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Po-Yen Hsu , Yi-Hsiu Chen , Ting-Ying Shen , Bo-Lun Wu , Meng-Hung Lin
IPC: H01L45/00
CPC classification number: H01L45/1266 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/124 , H01L45/146
Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.
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公开(公告)号：US09443587B1
公开(公告)日：2016-09-13
申请号：US14804354
申请日：2015-07-21
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Meng-Hung Lin , Ping-Kun Wang , Shao-Ching Liao , Chuan-Sheng Chou
CPC classification number: G11C13/0069 , G11C13/0064 , G11C2013/0066 , G11C2013/0073 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092
Abstract: A resistive memory apparatus and a writing method thereof are provided. In the method, logic data is received, and a corresponding resistive memory cell is selected. A logic level of the logic data is determined. When the logic data is in a first logic level, where a first reading current of the corresponding resistive memory cell is greater than a first reference current, a set pulse and a reset pulse are provided to the resistive memory cell during a writing period. When the logic data is in a second logic level, where a second reading current of the resistive memory cell is smaller than a second reference current, the reset pulse is provided to the resistive memory cell during the writing period. Polarities of the reset pulse and the set pulse are opposite.
Abstract translation: 提供了一种电阻式存储装置及其写入方法。 在该方法中，接收逻辑数据，并且选择相应的电阻性存储单元。 确定逻辑数据的逻辑电平。 当逻辑数据处于第一逻辑电平（其中对应的电阻性存储单元的第一读取电流大于第一参考电流）时，在写入周期期间将设置脉冲和复位脉冲提供给电阻存储器单元。 当逻辑数据处于第二逻辑电平时，其中电阻存储单元的第二读取电流小于第二参考电流，在写入周期期间将复位脉冲提供给电阻存储单元。 复位脉冲和设定脉冲的极性相反。
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公开(公告)号：US20230282279A1
公开(公告)日：2023-09-07
申请号：US17683356
申请日：2022-03-01
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Chia-Hung Lin , Jun-Yao Huang
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0007 , G11C2013/0045
Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether increasing rate of saturating read current is less than first threshold value; when increasing rate of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether increasing rate of saturating read current is less than first threshold value; finishing the method when increasing rate of saturating read current is less than first threshold value and saturating read current reaches target current value.
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公开(公告)号：US20220399490A1
公开(公告)日：2022-12-15
申请号：US17344963
申请日：2021-06-11
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen
Abstract: Provided is a memory device including a stack structure, a plurality of channel layers, a source line, a bit line, a switching layer, and a dielectric pillar. The stack structure has a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel layers are respectively embedded in the conductive layers. The source line penetrates through the stack structure to be electrically connected to the channel layers at first sides of the channel layers. The bit line penetrates through the stack structure to be coupled to the channel layers at second sides of the channel layers. The switching layer wraps the bit line to contact the channel layers at the second sides of the channel layers. The dielectric pillar penetrates through the channel layers to divide each channel layer into a doughnut shape. A method of manufacturing a memory device is also provided.
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公开(公告)号：US20220328513A1
公开(公告)日：2022-10-13
申请号：US17227383
申请日：2021-04-12
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Riichiro Shirota
IPC: H01L27/11582 , H01L27/11556 , H01L27/1157 , H01L27/11524
Abstract: A memory device and method of fabricating the same are provided. The memory device includes a substrate, a stacked structure, a channel layer, and a charge storage structure. The stacked structure is located on the substrate and includes a plurality of insulating layers and a plurality of conductive layers stacked alternately, and the stacked structure has holes. The channel layer is located in the hole and includes a first part and a second part. The number of grain boundaries in the second part is less than the number of grain boundaries in the first part. The charge storage structure is located between the first part and the plurality of conductive layers, and the charge storage structure and the second part sandwich the first part therebetween.
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Patent Agency Ranking
公开(公告)号：US11011231B2
公开(公告)日：2021-05-18
申请号：US16849976
申请日：2020-04-15
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Chang-Tsung Pai , Yu-Ting Chen , He-Hsuan Chao , Ming-Che Lin , Frederick Chen
Abstract: A data write-in method and a non-volatile memory are provided. The data write-in method includes: providing a reset voltage to a plurality of selected memory cells according to a first flag, and recursively performing a reset process for the plurality of selected memory cells; setting a second flag according to a plurality of first verification currents of the plurality of selected memory cells; and under a condition that the second flag is set: providing a set voltage to the plurality of selected memory cells according to a resistance of the plurality of selected memory cells; and setting the first flag according to a plurality of second verification currents of the plurality of selected memory cells.
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公开(公告)号：US20210074356A1
公开(公告)日：2021-03-11
申请号：US16849976
申请日：2020-04-15
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Chang-Tsung Pai , Yu-Ting Chen , He-Hsuan Chao , Ming-Che Lin , Frederick Chen
IPC: G11C13/00
Abstract: A data write-in method and a non-volatile memory are provided. The data write-in method includes: providing a reset voltage to a plurality of selected memory cells according to a first flag, and recursively performing a reset process for the plurality of selected memory cells; setting a second flag according to a plurality of first verification currents of the plurality of selected memory cells; and under a condition that the second flag is set: providing a set voltage to the plurality of selected memory cells according to a resistance of the plurality of selected memory cells; and setting the first flag according to a plurality of second verification currents of the plurality of selected memory cells.
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公开(公告)号：US10230047B2
公开(公告)日：2019-03-12
申请号：US14920635
申请日：2015-10-22
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen
Abstract: An RRAM device is provided, which includes a bottom electrode in an oxide layer, a plurality of dielectric protrusions on the oxide layer, wherein the bottom electrode is disposed between the two adjacent dielectric protrusions. A resistive switching layer is conformally disposed on the dielectric protrusions, the oxide layer, and the bottom electrode. A conductive oxygen reservoir layer is disposed on the resistive switching layer, and an oxygen diffusion barrier layer is disposed on the conductive oxygen reservoir layer.
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公开(公告)号：US20190027683A1
公开(公告)日：2019-01-24
申请号：US16129764
申请日：2018-09-12
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen
Abstract: The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.
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公开(公告)号：US10157962B2
公开(公告)日：2018-12-18
申请号：US14726626
申请日：2015-06-01
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao
Abstract: A resistive random access memory is provided. The resistive memory cell includes a substrate, a transistor on the substrate, a bottom electrode on the substrate and electrically connected to the transistor source/drain, several top electrodes on the bottom electrode, several resistance-switching layers between the top and bottom electrode, and several current limiting layers between the resistance-switching layer and top electrodes. The cell could improve the difficulty on recognizing 1/0 signal by current at high temperature environment and save the area on the substrate by generating several conductive filaments at one transistor location.
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