公开(公告)号：US20120256253A1

公开(公告)日：2012-10-11

申请号：US13432485

申请日：2012-03-28

申请人： Sung-Min Hwang ,  Woon-Kyung Lee ,  Young-Jin Kwon ,  Tae-Hee Lee ,  Hui-Chang Moon

发明人： Sung-Min Hwang ,  Woon-Kyung Lee ,  Young-Jin Kwon ,  Tae-Hee Lee ,  Hui-Chang Moon

IPC分类号： H01L29/78

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/7827

摘要： Vertical memory devices include a channel, a ground selection line (GSL), a word line, a string selection line (SSL), a pad and an etch-stop layer. The channel extends in a first direction on a substrate. The channel includes an impurity region and the first direction is perpendicular to a top surface of the substrate. At least one GSL, a plurality of the word lines and at least one SSL are spaced apart from each other in the first direction on a sidewall of the channel. The pad is disposed on a top surface of the channel. The etch-stop layer contacts the pad.

摘要翻译： 垂直存储器件包括通道，接地选择线（GSL），字线，串选择线（SSL），焊盘和蚀刻停止层。 通道在基板上沿第一方向延伸。 通道包括杂质区，第一方向垂直于衬底的顶表面。 至少一个GSL，多个字线和至少一个SSL在信道的侧壁上沿第一方向彼此间隔开。 衬垫设置在通道的顶表面上。 蚀刻停止层接触焊盘。

公开(公告)号：US08243518B2

公开(公告)日：2012-08-14

申请号：US12424135

申请日：2009-04-15

申请人： Dong-Yean Oh ,  Woon-Kyung Lee ,  Seung-Chul Lee

发明人： Dong-Yean Oh ,  Woon-Kyung Lee ,  Seung-Chul Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3454

摘要： An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.

摘要翻译： 集成电路包括一个包括串选择晶体管SST的NAND串和设置在串联存储单元MC的任一端的接地选择晶体管GST。 每个存储器存储单元是具有浮置栅极的存储晶体管，并且串选择晶体管SST和接地选择晶体管GST中的至少一个是具有浮置栅极的存储晶体管。 可编程串选择晶体管SST和接地选择晶体管GST的阈值电压Vth是可变的并且用户可控，并且不需要在制造期间通过注入建立。 存储器块中的每个可编程串选择晶体管SST和接地选择晶体管GST可用于存储随机数据，从而增加闪存器件的存储器存储容量。

公开(公告)号：US20120007193A1

公开(公告)日：2012-01-12

申请号：US13240575

申请日：2011-09-22

申请人： Jin-Sung Lee ,  Woon-Kyung Lee

发明人： Jin-Sung Lee ,  Woon-Kyung Lee

IPC分类号： H01L27/088

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573

摘要： A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed between adjacent transistors.

摘要翻译： 半导体器件包括设置在半导体衬底上的多个晶体管，围绕晶体管设置的器件隔离层，设置成围绕器件隔离层和晶体管的保护环以及设置在相邻晶体管之间的保护区。

公开(公告)号：US07847332B2

公开(公告)日：2010-12-07

申请号：US11615098

申请日：2006-12-22

申请人： Woon-Kyung Lee

发明人： Woon-Kyung Lee

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A nonvolatile memory device includes an active region defined by a device isolation layer in a semiconductor substrate, a word line passing over the active region and a charge storage region defined by a crossing of the active region and the word line and disposed between the active region and the word line. The charge storage region is disposed at an oblique angle with respect to the word line.

摘要翻译： 非易失性存储器件包括由半导体衬底中的器件隔离层限定的有源区，通过有源区的字线和由有源区和字线的交叉限定的电荷存储区，并且设置在有源区 和字线。 电荷存储区域相对于字线倾斜设置。

公开(公告)号：US07397130B2

公开(公告)日：2008-07-08

申请号：US11481503

申请日：2006-07-06

申请人： Woon-Kyung Lee

发明人： Woon-Kyung Lee

IPC分类号： H01L23/48

CPC分类号： H01L21/76897

摘要： A method of forming a semiconductor device can include forming a plurality of gate structure patterns including gates and first mask patterns stacked on a semiconductor substrate, the gate structure patterns being spaced apart from each other and extending in a first direction, forming a first interlayer insulating layer covering the gate structure patterns, forming a plurality of second mask patterns extending in a second direction crossing the first direction and spaced apart from each other, and etching the first interlayer insulating layer to form a contact hole, self-aligned to the first and second mask patterns, in at least one contact region defined by a neighboring pair of the first mask patterns and a neighboring pair of the second mask patterns. Related devices are also disclosed.

摘要翻译： 形成半导体器件的方法可以包括形成多个栅极结构图案，其包括在半导体衬底上堆叠的栅极和第一掩模图案，栅极结构图案彼此间隔开并沿第一方向延伸，形成第一层间绝缘 覆盖所述栅极结构图案，形成沿与所述第一方向交叉的第二方向延伸并且彼此间隔开的多个第二掩模图案，并且蚀刻所述第一层间绝缘层以形成与所述第一和第二绝缘层自对准的接触孔， 在由相邻对的第一掩模图案定义的至少一个接触区域和相邻的第二掩模图案对中的第二掩模图案。 还公开了相关设备。

公开(公告)号：US20080081414A1

公开(公告)日：2008-04-03

申请号：US11651538

申请日：2007-01-10

申请人： Woon-Kyung Lee ,  Jong-Kwang Lim

发明人： Woon-Kyung Lee ,  Jong-Kwang Lim

IPC分类号： H01L21/336

CPC分类号： H01L27/11531 ,  H01L27/105 ,  H01L27/11526

摘要： A method for fabricating a nonvolatile memory device comprises providing a substrate, forming an insulating layer and a conductive layer on the substrate, forming an electrical connection path out of a portion of the conductive layer, through which the conductive layer is electrically connected to the substrate, and gate patterning the insulating layer and the conductive layer.

摘要翻译： 一种用于制造非易失性存储器件的方法包括在衬底上提供衬底，形成绝缘层和导电层，在导电层的一部分中形成电连接路径，导电层通过该导电层电连接到衬底 ，并且对图案化绝缘层和导电层的栅极。

公开(公告)号：US20060214215A1

公开(公告)日：2006-09-28

申请号：US11434128

申请日：2006-05-16

申请人： Woon-Kyung Lee

发明人： Woon-Kyung Lee

IPC分类号： H01L29/76 ,  H01L29/00

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/11568

摘要： The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

摘要翻译： 本发明提供一种其中栅极与器件隔离膜自对准的半导体器件及其制造方法。 限制有源区的器件隔离膜设置在半导体衬底的一部分上，并且字线跨过器件隔离膜。 栅极图案设置在字线和有源区之间，并且隧道氧化膜设置在栅极图案和有源区之间。 栅极图案包括以相应顺序沉积的浮置栅极图案，栅极层间电介质膜图案和控制栅极电极图案，并且具有与器件隔离膜自对准的侧壁。 为了形成具有与器件隔离膜自对准的侧壁的栅极图案，在半导体衬底上分别形成栅极绝缘膜和栅极材料膜。

公开(公告)号：US06855978B2

公开(公告)日：2005-02-15

申请号：US10299535

申请日：2002-11-18

申请人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

发明人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L29/788

CPC分类号： H01L21/76897 ,  H01L21/76895

摘要： A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole. Accordingly, the interlayer insulation layer pattern is intervened between the gate contact plug and a sidewall of the capping pattern.

公开(公告)号：US06635532B2

公开(公告)日：2003-10-21

申请号：US10099126

申请日：2002-03-15

申请人： Yun-Heub Song ,  Woon-Kyung Lee

发明人： Yun-Heub Song ,  Woon-Kyung Lee

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Disclosed is a method for fabricating a NOR flash memory device where a buried common source line made of an impurity diffusion layer has an even surface or a lower step difference. The method includes forming adjacent isolation layers that define an active region there between within a semiconductor substrate. Then, a floating gate pattern is formed overlying the active region. An inter-gate dielectric film and a control gate film are sequentially formed overlying the floating gate pattern. The control gate film, the inter-gate dielectric film, and the floating gate pattern are sequentially patterned, thereby forming a plurality of word lines extending across the active region. The active region between the adjacent isolation layers and the isolation layers are removed, adjacent to one sidewall of the word lines, thereby forming a common source line region. Next, impurities are implanted into the common source line region, thereby forming a common source line made of an impurity diffusion layer.

公开(公告)号：US6150700A

公开(公告)日：2000-11-21

申请号：US232685

申请日：1999-01-19

申请人： Woon-Kyung Lee

发明人： Woon-Kyung Lee

IPC分类号： G11C17/12 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11293 ,  H01L27/112

摘要： A NOR-type mask ROM includes a semiconductor substrate of a first conductivity type. A plurality of buried diffusion regions of a second conductivity type opposite to the first conductivity type are arranged in parallel on the substrate to serve as sources and drains. A plurality of channel regions are defined between the buried diffusion regions and a plurality of gate insulating layers are formed on the channel regions. A plurality of gate regions are formed in parallel on the gate insulating layers, intersecting the buried diffusion regions, and overlapping with the channel regions, to be provided as word lines. An insulating layer is deposited on the overall surface of the substrate, covering the gate regions, and a plurality of sub-gate regions are formed into spacers on the sidewalls of the insulating layer, in parallel with the gate regions, for increasing a cell current.

摘要翻译： NOR型掩模ROM包括第一导电类型的半导体衬底。 与第一导电类型相反的第二导电类型的多个掩埋扩散区域平行布置在衬底上以用作源极和漏极。 在掩埋扩散区域之间限定多个通道区域，并且在沟道区域上形成多个栅极绝缘层。 多个栅极区域平行地形成在栅极绝缘层上，与掩埋的扩散区域相交并与沟道区域重叠，以作为字线提供。 绝缘层沉积在衬底的整个表面上，覆盖栅极区域，并且多个子栅极区域与栅极区域平行地形成在绝缘层的侧壁上的间隔物中，以增加电池电流 。