公开(公告)号：US4291274A

公开(公告)日：1981-09-22

申请号：US096056

申请日：1979-11-20

申请人： Yasoji Suzuki ,  Nobuyuki Kamimaru

发明人： Yasoji Suzuki ,  Nobuyuki Kamimaru

IPC分类号： G01R25/00 ,  H02N2/06 ,  H03D13/00 ,  H03K5/26

CPC分类号： H03D13/004 ,  G01R25/005

摘要： A phase detector circuit having four dominant type flip-flop circuits and at least one logic gate. The phase detector circuit is responsive to changes of two input signals, and produces output signals related to the relative phase of the input signals having duty cycle. The output signals have a predetermined level only for the period the phases of the input signals differ. When the phases of the input signals are the same, the output signals of the phase detector circuit will be at another level.

摘要翻译： 一种具有四个显性触发器电路和至少一个逻辑门的相位检测器电路。 相位检测器电路响应两个输入信号的变化，并且产生与具有占空比的输入信号的相对相关的输出信号。 输出信号仅在输入信号的相位不同的周期内具有预定电平。 当输入信号的相位相同时，相位检测器电路的输出信号将处于另一级。

公开(公告)号：US4230951A

公开(公告)日：1980-10-28

申请号：US882147

申请日：1978-02-28

申请人： Yasoji Suzuki ,  Susumu Kouyama

发明人： Yasoji Suzuki ,  Susumu Kouyama

IPC分类号： G11C27/04 ,  G11C19/28 ,  H03H11/26 ,  H03K5/15

CPC分类号： H03K5/15013 ,  G11C19/282

摘要： A plurality of signal lines receiving signals with different phases are connected to the reference potential point through switching elements. The switching elements connected to signal lines other than the signal line receiving an active signal are rendered conductive by the active signal on the signal line and the other signal lines are led to the reference potential.

摘要翻译： 接收不同相位的信号的多条信号线通过开关元件连接到参考电位点。 连接到接收有源信号的信号线以外的信号线的开关元件由信号线上的有源信号导通，其他信号线被引导到参考电位。

公开(公告)号：US4217535A

公开(公告)日：1980-08-12

申请号：US864085

申请日：1977-12-23

申请人： Yasoji Suzuki ,  Takeshi Hitotsuyanagi ,  Tetsuya Iida

发明人： Yasoji Suzuki ,  Takeshi Hitotsuyanagi ,  Tetsuya Iida

IPC分类号： G01R31/36 ,  G05F3/24 ,  H02J7/10 ,  H03K3/26

CPC分类号： G01R19/16542 ,  G05F3/245 ,  G05F3/247

摘要： A constant-voltage circuit in which a diode and an MOS transistor are connected in series between power supply terminals between which a battery power source is connected. The MOS transistor is biased to operate in the saturation region. The forward voltage drop across the diode is kept substantially constant independent of variations in battery voltage and temperature. This constant-voltage circuit may preferably be used in a battery checker circuit for detecting the end of battery life.

摘要翻译： 一种恒压电路，其中二极管和MOS晶体管串联连接在其上连接有电池电源的电源端子之间。 MOS晶体管被偏置以在饱和区域中工作。 独立于电池电压和温度的变化，二极管两端的正向压降保持基本恒定。 这种恒压电路可以优选地用于检测电池寿命结束的电池检查电路中。

公开(公告)号：US4217502A

公开(公告)日：1980-08-12

申请号：US941256

申请日：1978-09-11

申请人： Yasoji Suzuki ,  Ryuzo Shiraki

发明人： Yasoji Suzuki ,  Ryuzo Shiraki

IPC分类号： H03K19/0185 ,  H03K19/094 ,  H03K19/20 ,  H03K17/04 ,  H03K19/08

CPC分类号： H03K19/09429 ,  H03K19/018521

摘要： An output circuit is provided in which a first IG-FET of a first conductivity type is connected between a first potential supply terminal and an output terminal and having its substrate controlled by a third potential higher than the first potential of the first potential supply terminal and a second IG-FET of a second conductivity type connected between a second potential supply terminal having a second potential lower than the first potential and the output terminal and having its substrate electrode supplied with the second potential. A control circuit is further provided which receives an input signal and control signal and controls the output circuit to permit the latter to produce one of the first potential, second potential and high impedance state. The output circuit and control circuit are combined to provide a converter circuit for converting the level of a CML (complementary MOS Transistor Logic) to a TTL (Transistor-Transistor Logic). A compensation circuit is further provided which, when a potential on the output terminal is shifted from the second potential to the first potential, permits a rise of the second potential to be sharpened. The compensation circuit includes a third IG-FET of a second conductivity type connected between the first potential supply terminal and the output terminal.

摘要翻译： 提供了一种输出电路，其中第一导电类型的第一IG-FET连接在第一电位供给端子和输出端子之间，并且其基板受到比第一电位供应端子的第一电位高的第三电位的控制， 第二导电类型的第二IG-FET连接在具有低于第一电位的第二电位的第二电位供应端和输出端之间，并且其基板电极被提供有第二电位。 还提供控制电路，其接收输入信号和控制信号，并控制输出电路以允许输出信号产生第一电位，第二电位和高阻抗状态之一。 输出电路和控制电路被组合以提供用于将CML（互补MOS晶体管逻辑）的电平转换为TTL（晶体管 - 晶体管逻辑）的转换器电路。 还提供补偿电路，当输出端子上的电位从第二电位移动到第一电位时，允许第二电位的上升被削尖。 补偿电路包括连接在第一电位供给端子和输出端子之间的第二导电类型的第三IG-FET。

公开(公告)号：US4209830A

公开(公告)日：1980-06-24

申请号：US932400

申请日：1978-08-09

申请人： Yoshiaki Arimura ,  Hideharu Egawa ,  Yasoji Suzuki

发明人： Yoshiaki Arimura ,  Hideharu Egawa ,  Yasoji Suzuki

IPC分类号： G06T7/00 ,  G06F15/46

CPC分类号： G06T7/0042

摘要： A position and direction sensing mark is formed on an integrated circuit pellet formed with a prescribed electrode pattern. The position and direction sensing mark comprises a plurality of strips which are extended in a direction different from that in which the electrode pattern is extended and are arranged in turn at prescribed intervals in a direction intersecting the different direction at right angles thereto.

摘要翻译： 位置和方向检测标记形成在形成有规定电极图案的集成电路芯片上。 位置和方向检测标记包括沿与电极图案延伸的方向不同的方向延伸的多个条带，并且在与其不同的方向交叉的方向上以规定的间隔依次布置。

公开(公告)号：US4151610A

公开(公告)日：1979-04-24

申请号：US777664

申请日：1977-03-15

申请人： Yasoji Suzuki ,  Kiyofumi Ochii

发明人： Yasoji Suzuki ,  Kiyofumi Ochii

IPC分类号： G11C11/404 ,  G11C11/406 ,  H01L27/108 ,  G11C11/24 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C11/404 ,  G11C11/406 ,  H01L27/10805

摘要： A semiconductor memory device comprising an N conductivity type semiconductor substrate, a P conductivity type well formed in a specified section of the surface of the semiconductor substrate, N conductivity type source and drain regions formed in the P conductivity type well, and a gate insulation layer deposited on the surface of the well over the source and drain regions. The P conductivity type well has a higher impurity concentration than the N conductivity type semiconductor substrate and the N conductivity type source and drain regions have a higher impurity concentration than the P conductivity type well. An insulation film is formed on the drain region and the insulation film, a metal electrode layer deposited on the insulation film and drain region collectively institute a capacitor.

摘要翻译： 一种半导体存储器件，包括N导电型半导体衬底，在半导体衬底的表面的特定部分中良好地形成的P导电型，在P导电型阱中形成的N导电型源极和漏极区域以及栅极绝缘层 沉积在源极和漏极区上的阱的表面上。 P导电类型的阱具有比N导电型半导体衬底更高的杂质浓度，并且N导电型源区和漏区具有比P导电类型井更高的杂质浓度。 在漏极区域和绝缘膜上形成绝缘膜，沉积在绝缘膜和漏极区域上的金属电极层共同构成电容器。

公开(公告)号：US4103345A

公开(公告)日：1978-07-25

申请号：US680236

申请日：1976-04-26

申请人： Yasoji Suzuki ,  Kiyofumi Ochii

发明人： Yasoji Suzuki ,  Kiyofumi Ochii

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/06

CPC分类号： G11C11/412 ,  G11C11/419

摘要： Provided is a semiconductor memory device comprising a pair of data input lines, a pair of data output lines, memory cells arranged in the form of a matrix, the memory cell of each column being connected between a pair of data lines, the memory cell of each row being connected to a row selection line, a memory cell selection circuit for generating column and row designation signals in order to select a desired one of said memory cells, a switching circuit disposed in each column and turned on upon receipt of a column designation signal from the memory cell selection circuit to connect the data line to a corresponding one of the data input lines, and a data detection circuit connected between the pair of data lines of each column and adapted, upon receipt of a column signal from the memory cell selection circuit, to transmit an inverted signal of a signal on the data line onto the data output line.

公开(公告)号：US3947829A

公开(公告)日：1976-03-30

申请号：US491477

申请日：1974-07-22

申请人： Yasoji Suzuki

发明人： Yasoji Suzuki

IPC分类号： G11C19/28 ,  H03K19/00 ,  H03K19/096 ,  G11C17/00

CPC分类号： H03K19/0963

摘要： A plurality of logical control circuits each having a storage or delay function are driven by a writing-in clock pulse .phi.1 and a reading-out clock pulse .phi.2 supplied in common thereto and receiving output signals from a Read Only Memory constructed in the form of a matrix. This Read Only Memory is constituted by a plurality of logical gate circuits each supplied with a plurality of prescribed signals of a pulse signal group having a plurality of input signals I1, I2, . . . In and control pulse signals T8, D4, A and B different in frequency from the clock pulses .phi.1 and .phi.2. The logical control circuit includes a first logical gate supplied with a feed back signal from the logical control circuit and a prescribed control pulse signal and a second logical gate supplied with an output signal generated from the corresponding logical gate circuit of the Read Only Memory in accordance with the prescribed control pulse signal and prescribed input signals and with an output signal from the first logical gate the output of the second logical gate is delayed in response to clock pulses .phi.1 and .phi.2 and then is generated as an output signal from the logical control circuit.

摘要翻译： 每个具有存储或延迟功能的多个逻辑控制电路由共同提供的写入时钟脉冲phi 1和读出时钟脉冲phi 2驱动，并从形式的构造的只读存储器接收输出信号 的矩阵。 该只读存储器由多个逻辑门电路构成，每个逻辑门电路分别提供多个具有多个输入信号I1，I2的脉冲信号组的规定信号。 的。 的。 输入和控制频率与时钟脉冲phi 1和phi 2不同的脉冲信号T8，D4，A和B.逻辑控制电路包括提供有来自逻辑控制电路的反馈信号的第一逻辑门和规定的控制脉冲 信号和第二逻辑门，其提供有根据规定的控制脉冲信号和规定的输入信号从只读存储器的对应的逻辑门电路产生的输出信号，以及来自第一逻辑门的输出信号，第二逻辑门的​​输出 逻辑门被响应于时钟脉冲phi 1和phi 2延迟，然后被产生为来自逻辑控制电路的输出信号。

公开(公告)号：US5237201A

公开(公告)日：1993-08-17

申请号：US795257

申请日：1991-11-19

申请人： Toru Tanaki ,  Yasoji Suzuki

发明人： Toru Tanaki ,  Yasoji Suzuki

IPC分类号： H01L23/495 ,  H05K1/02

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H05K1/0254

摘要： This invention provides a TAB type semiconductor device in which a plurality of lead pattern regions are formed on a film-like tape formed of an insulating resin, and LSI chips are inner lead-bonded onto the corresponding lead pattern regions. A linear reference potential supply wiring pattern is formed on one edge portion in the widthwise direction of a formation surface of the lead pattern regions on the tape to extend in the tape extending direction. The wiring pattern is electrically connected to a reference potential supply lead (14A) of each lead pattern region.

摘要翻译： 本发明提供了一种TAB型半导体器件，其中在由绝缘树脂形成的膜状带上形成多个引线图案区域，并且将LSI芯片内引线键合到相应的引线图案区域。 在带的引线图案区域的形成面的宽度方向的一个边缘部分上形成线性参考电位供给布线图案，以沿带延伸方向延伸。 布线图案电连接到每个引线图案区域的参考电位供应引线（14A）。

公开(公告)号：US5027012A

公开(公告)日：1991-06-25

申请号：US480898

申请日：1990-02-16

申请人： Yukihiro Saeki ,  Yasoji Suzuki

发明人： Yukihiro Saeki ,  Yasoji Suzuki

IPC分类号： H03K19/20 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17704 ,  H03K19/1731

摘要： A programmable logic circuit for deriving a logic output of first and second signals includes a 2-input logic gate for deriving a logic output of two signals. The 2-input logic gate is constituted by connecting two 3-state circuits in a wired OR configuration. One of the 3-state circuits includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives an inverted signal of the second signal, and the data output terminal is set to one of three states of "1", "0", and the high impedance. Likewise, the other 3-state circuit includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives the second signal, and the data output terminal is set to one of three states of "1", "0", and the high impedance. Each of the data input terminals of the 3-state circuits is supplied with a desired one of the first signal, an inverted signal of the first signal, a "0" level signal, and a "1" level signal in a programmable fashion. Various logic gates can be realized by programming the supplying states of the four signals.