公开(公告)号：US20100097246A1

公开(公告)日：2010-04-22

申请号：US12579903

申请日：2009-10-15

申请人： Kazutoshi WATANABE ,  Hideaki Nagakubo ,  Takenobu Kimura ,  Koichi Yamamoto ,  Katsuyki Katayama ,  Naomi Sato ,  Naoya Akiyama ,  Shinichiro Kimura ,  Masahiro Ishida ,  Naoki Yamada ,  Keiji Takagi ,  Toshinobu Hosaka

发明人： Kazutoshi WATANABE ,  Hideaki Nagakubo ,  Takenobu Kimura ,  Koichi Yamamoto ,  Katsuyki Katayama ,  Naomi Sato ,  Naoya Akiyama ,  Shinichiro Kimura ,  Masahiro Ishida ,  Naoki Yamada ,  Keiji Takagi ,  Toshinobu Hosaka

IPC分类号： H03M11/00

CPC分类号： G06F3/0202 ,  H01H13/83 ,  H01H2219/044 ,  H01H2219/056 ,  H01H2219/06 ,  H01H2219/062

摘要： An input device includes a plurality of manipulation portions; an input function portion manipulated by the manipulation portions to perform an input function; a light guiding sheet facing the rear side of the plurality of manipulation portions; and a light source applying light into the light guiding sheet, wherein a rear surface opposite to a front surface of the light guiding sheet facing the manipulation portions is provided with a plurality of concave portions which is depressed to the inside of the light guiding sheet, wherein each concave portion has a circular opening and an inner surface which is a smooth concave curve surface, and wherein light propagated through the inside of the light guiding sheet is reflected by the inner surface toward the inside of the light guiding sheet, and the light is applied from the front surface of the light guiding sheet to the manipulation portions.

摘要翻译： 输入装置包括多个操作部分; 由操作部分操纵以输入功能的输入功能部分; 面向所述多个操作部的后侧的导光片; 以及向所述导光片施加光的光源，其中与所述导光片的面对所述操作部的前表面相对的后表面设置有多个凹陷部，所述凹部被压向所述导光片的内部， 其特征在于，每个凹部具有圆形开口和内表面，该内表面是光滑的凹曲面，并且其中通过导光片的内部传播的光被内表面朝向导光片的内部反射，并且光 从导光片的前表面施加到操作部。

公开(公告)号：US20100084709A1

公开(公告)日：2010-04-08

申请号：US11993862

申请日：2006-06-30

申请人： Ryuta Tsuchiya ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Shinichiro Kimura

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/86

CPC分类号： H01L27/12 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1207

摘要： When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate, the SOI-type MISFET and the bulk-type MISFET should be formed in separate steps respectively, and thus the process gets complicated. A single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) are used, and well diffusion layer regions, drain regions, gate insulating films and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in same steps. Since the bulk-type MISFET and the SOI-type MISFET can be formed on the same substrate, the board area can be reduced. A simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

摘要翻译： 当单独使用体硅衬底和SOI衬底时，板面积增加，因此整体上不可能减小半导体器件的尺寸。 另一方面，当在同一衬底上形成SOI型MISFET和体型MISFET时，分别将SOI型MISFET和体型MISFET分别形成，因此工艺变得复杂。 使用通过薄埋入绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的单晶半导体衬底和SOI衬底，以及良好扩散层区域，漏极区域，栅极绝缘膜 并且以相同的步骤形成SOI型MISFET和体型MISFET的栅电极。 由于可以在同一基板上形成体型MISFET和SOI型MISFET，所以可以减小电路板面积。 可以通过制造SOI型MISFET和体型MISFET的制造步骤来实现简单的工艺。

公开(公告)号：US20080258218A1

公开(公告)日：2008-10-23

申请号：US12105226

申请日：2008-04-17

申请人： Yusuke Morita ,  Yoshinobu Kimura ,  Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Shinichiro Kimura

发明人： Yusuke Morita ,  Yoshinobu Kimura ,  Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Shinichiro Kimura

IPC分类号： H01L27/01

CPC分类号： H01L29/045 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

摘要： A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface of the substrate and respectively having one edge positioned under the sidewall of the gate electrode; a first stacked layer formed on the source/drain semiconductor regions and in contact with the first sidewall insulating film; a second sidewall insulating film formed on the stacked layer and in contact with the first sidewall insulating film; and a second stacked layer formed on the first stacked layer and in contact with the second sidewall insulating layer.

摘要翻译： 提供了具有倾斜堆叠的源极/漏极结构的MIS晶体管，其速度提高。 MIS晶体管包括：形成在衬底上的栅电极; 形成在所述基板上并沿着所述栅电极的侧壁的第一侧壁绝缘膜; 源极/漏极半导体区域，形成在基板的主表面上，并且分别具有位于栅电极的侧壁下方的一个边缘; 形成在所述源极/漏极半导体区域上并与所述第一侧壁绝缘膜接触的第一堆叠层; 形成在所述层叠层上并与所述第一侧壁绝缘膜接触的第二侧壁绝缘膜; 以及形成在第一堆叠层上并与第二侧壁绝缘层接触的第二堆叠层。

公开(公告)号：US20060081836A1

公开(公告)日：2006-04-20

申请号：US11249681

申请日：2005-10-14

申请人： Yoshinobu Kimura ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Ryuta Tsuchiya ,  Shinichi Saito

发明人： Yoshinobu Kimura ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Ryuta Tsuchiya ,  Shinichi Saito

IPC分类号： H01L31/109

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7835

摘要： In a field effect semiconductor device for high frequency power amplification, it is difficult to achieve size reduction and increased efficiency simultaneously while ensuring voltage withstanding. A further improvement in efficiency is attained by using a strained Si channel for LDMOS at an output stage for high frequency power amplification. Further, the efficiency is improved as much as possible while decreasing a leak current, by optimizing the film thickness of the strained Si layer having a channel region, inactivation of defects and a field plate structure.

摘要翻译： 在用于高频功率放大的场效半导体器件中，难以在确保耐压的同时实现尺寸减小和提高效率。 通过在高频功率放大的输出级使用用于LDMOS的应变Si通道来实现效率的进一步提高。 此外，通过优化具有通道区域的应变Si层的膜厚度，缺陷的失活和场板结构，尽可能地提高效率同时减小漏电流。

公开(公告)号：US06867090B2

公开(公告)日：2005-03-15

申请号：US10421903

申请日：2003-04-24

申请人： Masahiko Hiratani ,  Shinichiro Kimura ,  Tomoyuki Hamada

发明人： Masahiko Hiratani ,  Shinichiro Kimura ,  Tomoyuki Hamada

IPC分类号： C23C16/40 ,  H01L21/02 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/02194 ,  H01L21/02183 ,  H01L21/02192 ,  H01L21/02271 ,  H01L21/31604 ,  H01L21/31691 ,  H01L27/10814 ,  H01L28/40

摘要： By using a solid solution of tantalum pentoxide and niobium pentoxide as a dielectric film installed between upper electrode and lower electrode in a capacitor which is used in a semiconductor device, the capacitor structure can be simplified to improve reliability of the semiconductor device while reducing the production cost thereof.

摘要翻译： 通过使用五氧化二钽和五氧化铌的固溶体作为安装在半导体器件中的电容器中的上电极和下电极之间的电介质膜，可以简化电容器结构以提高半导体器件的可靠性，同时减少生产 成本。

公开(公告)号：US06770535B2

公开(公告)日：2004-08-03

申请号：US09767830

申请日：2001-01-24

申请人： Satoru Yamada ,  Kiyonori Oyu ,  Shinichiro Kimura

发明人： Satoru Yamada ,  Kiyonori Oyu ,  Shinichiro Kimura

IPC分类号： H01L21336

CPC分类号： H01L27/10876 ,  H01L21/763 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： A reduction of the junction electric field intensity is accomplished in the semiconductor regions for the sources and drains of field effects transistors. For this purpose, a structure is provided where the gate electrodes 9 of the MIS.FETQs for memory cell selection of a DRAM are buried within the trenches 7a and 7b created in the semiconductor substrate 1. The bottom corners within the trench 7b are rounded so as to have a radius of curvature in accordance with the sub-threshold coefficient of the MIS.FETQs for memory cell selection. In addition, the gate insulating film 8 within the trench 7b is made to have a laminated structure of a thermal oxide film and a CVD film.

摘要翻译： 在场效应晶体管的源极和漏极的半导体区域中实现结电场强度的降低。 为此，提供了一种结构，其中用于DRAM的存储单元选择的MIS.FETQ的栅电极9被埋在在半导体衬底1中形成的沟槽7a和7b内。沟槽7b内的底角被倒圆 具有根据用于存储器单元选择的MIS.FETQ的子阈值系数的曲率半径。 此外，使沟槽7b内的栅极绝缘膜8具有热氧化膜和CVD膜的层叠结构。

公开(公告)号：US06576928B2

公开(公告)日：2003-06-10

申请号：US09930144

申请日：2001-08-16

申请人： Masahiko Hiratani ,  Shinichiro Kimura ,  Tomoyuki Hamada

发明人： Masahiko Hiratani ,  Shinichiro Kimura ,  Tomoyuki Hamada

IPC分类号： H01L27108

CPC分类号： H01L21/02194 ,  H01L21/02183 ,  H01L21/02192 ,  H01L21/02271 ,  H01L21/31604 ,  H01L21/31691 ,  H01L27/10814 ,  H01L28/40

摘要： By using a solid solution of tantalum pentoxide and niobium pentoxide as a dielectric film installed between upper electrode and lower electrode in a capacitor which is used in a semiconductor device, the capacitor structure can be simplified to improve reliability of the semiconductor device while reducing the production cost thereof.

摘要翻译： 通过使用五氧化二钽和五氧化铌的固溶体作为安装在半导体器件中的电容器中的上电极和下电极之间的电介质膜，可以简化电容器结构以提高半导体器件的可靠性，同时减少生产 成本。

公开(公告)号：US06498100B2

公开(公告)日：2002-12-24

申请号：US09996918

申请日：2001-11-30

申请人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

发明人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

IPC分类号： H01L21302

CPC分类号： H01L27/10894 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/10814

摘要： In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved. At the same time, upon chemical mechanical polishing, a silicon substrate can be prevented from being exposed at the central portion of the memory mat portion and the insulating film can be prevented from being left on the silicon nitride film near the outer periphery, thereby making it possible to form elements having uniform electrical characteristics on all active regions of the memory mat portion.

公开(公告)号：US5591998A

公开(公告)日：1997-01-07

申请号：US443106

申请日：1995-05-17

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

公开(公告)号：US5583358A

公开(公告)日：1996-12-10

申请号：US324352

申请日：1994-10-17

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。