公开(公告)号：US20120091452A1

公开(公告)日：2012-04-19

申请号：US13377824

申请日：2010-03-10

申请人： Yoshifumi Ohta ,  Go Mori ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Takeshi Hara

发明人： Yoshifumi Ohta ,  Go Mori ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Takeshi Hara

IPC分类号： H01L29/786 ,  H01L21/34

CPC分类号： H01L29/22 ,  G02F1/1368 ,  G02F2202/10 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

摘要： The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.

摘要翻译： 本发明提供一种能够实现具有稳定晶体管特性的薄膜晶体管的氧化物半导体，具有由氧化物半导体形成的沟道层的薄膜晶体管及其制造方法，以及配备有该薄膜晶体管的显示装置。 本发明的氧化物半导体是薄膜晶体管的氧化物半导体。 氧化物半导体包括铟，镓，锌和氧作为构成原子，并且氧化物半导体的氧含量为化学计量条件的87％至95％，以原子单位计为100％。

公开(公告)号：US06982768B2

公开(公告)日：2006-01-03

申请号：US09797913

申请日：2001-03-01

申请人： Tatsuya Ohori ,  Michiko Takei ,  Hongyong Zhang ,  Hideomi Suzawa ,  Naoaki Yamaguchi

发明人： Tatsuya Ohori ,  Michiko Takei ,  Hongyong Zhang ,  Hideomi Suzawa ,  Naoaki Yamaguchi

IPC分类号： G02F1/136

CPC分类号： G02F1/136209

摘要： An active type liquid crystal display device, comprising an electrode being formed by using a transparent electrically conductive film constituting a pixel electrode, which allows the black matrix to be set as the common potential. Also claimed is an active type liquid crystal display device of the same type as above, comprising an electrode being formed on the same layer as that of the source line, which allows the black matrix to be set as the common potential.

摘要翻译： 一种主动型液晶显示装置，其特征在于，具有通过使用构成像素电极的透明导电膜形成的电极，其能够将黑矩阵设定为公共电位。 还要求保护的是与上述相同类型的有源型液晶显示装置，其包括形成在与源极线相同的层上的电极，其允许将黑矩阵设定为公共电位。

公开(公告)号：US06628349B1

公开(公告)日：2003-09-30

申请号：US09651876

申请日：2000-08-30

申请人： Michiko Takei ,  Yasuyoshi Mishima ,  Mitsuru Chida ,  Kohta Yoshikawa

发明人： Michiko Takei ,  Yasuyoshi Mishima ,  Mitsuru Chida ,  Kohta Yoshikawa

IPC分类号： G02F1136

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78645

摘要： A liquid crystal display substrate including gate and drain bus lines that are electrically insulated from each other at cross areas, pixel electrodes between the cross areas, and first thin film transistors connecting corresponding drain bus lines and pixel electrodes. Each first thin film transistor includes a channel region where current flows in a first direction, and first and second impurity doped regions of, respectively, first and second impurity concentrations. The first and second doped regions sandwich the channel region. The second impurity concentration is higher than the first. Also, a second thin film transistor is formed in the peripheral circuit area, and includes a channel region where current flows in a second direction that is perpendicular to the first direction. Third impurity doped regions, disposed on both sides of the channel region, have a third impurity concentration.

摘要翻译： 一种液晶显示基板，包括在交叉区域彼此电绝缘的栅极和漏极总线，以及交叉区域之间的像素电极和连接相应的漏极总线和像素电极的第一薄膜晶体管。 每个第一薄膜晶体管包括电流沿第一方向流动的沟道区，以及分别为第一和第二杂质浓度的第一和第二杂质掺杂区。 第一和第二掺杂区夹着沟道区。 第二杂质浓度高于第一杂质浓度。 此外，第二薄膜晶体管形成在外围电路区域中，并且包括电流沿与第一方向垂直的第二方向流动的沟道区域。 设置在沟道区两侧的第三杂质掺杂区具有第三杂质浓度。

公开(公告)号：US06239850B1

公开(公告)日：2001-05-29

申请号：US08841849

申请日：1997-05-05

申请人： Tatsuya Ohori ,  Michiko Takei ,  Hongyong Zhang ,  Jun Koyama

发明人： Tatsuya Ohori ,  Michiko Takei ,  Hongyong Zhang ,  Jun Koyama

IPC分类号： G02F11333

CPC分类号： G02F1/136204

摘要： A process of fabricating a liquid crystal electro-optical (display) device. The device includes discharge accelerating patterns extending from associated gate bus patterns and provided with a unique geometry. The disclosed geometry minimizes the dielectric breakdown of a gate insulating film attributable to plasma discharge between gate and source/drain electrodes of the associated thin film transistors.

摘要翻译： 一种制造液晶电光（显示）装置的方法。 该装置包括从关联的栅极总线图案延伸并且具有独特几何形状的放电加速图案。 所公开的几何形状最小化归因于相关联的薄膜晶体管的栅极和源极/漏极之间的等离子体放电的栅极绝缘膜的介电击穿。

公开(公告)号：US6025607A

公开(公告)日：2000-02-15

申请号：US842301

申请日：1997-05-05

申请人： Tatsuya Ohori ,  Michiko Takei ,  Hongyong Zhang ,  Yuugo Goto

发明人： Tatsuya Ohori ,  Michiko Takei ,  Hongyong Zhang ,  Yuugo Goto

IPC分类号： G02F1/1343 ,  G02F1/136 ,  G02F1/1368 ,  H01L21/266 ,  H01L21/336 ,  H01L29/786 ,  H01L31/0392

CPC分类号： H01L29/66757

摘要： A polysilicon pattern constituting an active portion of a TFT is formed on a substrate so as to be curved to generally assume a U shape, and a gate pattern is formed as a straight conductor pattern. The gate pattern is so disposed as to cross the U-shaped polysilicon pattern plural times. The silicon pattern comprise a plurality of channel regions and impurity regions of which alignment is symmetrical.

摘要翻译： 构成TFT的有源部分的多晶硅图案形成在基板上，以弯曲成大致呈U字状，并且栅极图案形成为直导体图案。 栅极图案被设置成多次跨越U形多晶硅图案。 硅图案包括多个通道区域和其对准的对称的杂质区域。

公开(公告)号：US08779478B2

公开(公告)日：2014-07-15

申请号：US13701028

申请日：2011-05-23

申请人： Masao Moriguchi ,  Michiko Takei ,  Yohsuke Kanzaki ,  Tsuyoshi Inoue ,  Tetsuo Fukaya ,  Yudai Takanishi ,  Takatsugu Kusumi ,  Yoshiki Nakatani ,  Tetsuya Okamoto ,  Kenji Nakanishi

发明人： Masao Moriguchi ,  Michiko Takei ,  Yohsuke Kanzaki ,  Tsuyoshi Inoue ,  Tetsuo Fukaya ,  Yudai Takanishi ,  Takatsugu Kusumi ,  Yoshiki Nakatani ,  Tetsuya Okamoto ,  Kenji Nakanishi

IPC分类号： H01L29/76 ,  H01L29/66 ,  H01L29/786 ,  H01L29/24

CPC分类号： H01L29/7869 ,  H01L29/24 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78696

摘要： A TFT 20 includes a gate electrode 21, a gate insulating film 22, a semiconductor layer 23, a source electrode 24, a drain electrode 25, etc. The semiconductor layer 23 is comprised of a metal oxide semiconductor (IGZO), and has a source portion 23a that contacts the source electrode 24, a drain electrode 23b that contacts the drain electrode 25, and a channel portion 23c that is located between the source and drain portions 23a, 23b. A reduced region 30 is formed at least in the channel portion 23c of the semiconductor layer 23, and the reduced region 30 has a higher content of a simple substance of a metal such as In than the remaining portion of the semiconductor layer 23.

摘要翻译： TFT20包括栅极电极21，栅极绝缘膜22，半导体层23，源极24，漏极电极25等。半导体层23由金属氧化物半导体（IGZO）构成，具有 与源电极24接触的源部23a，与漏电极25接触的漏电极23b和位于源极部23a，第二漏极23b之间的沟道部23c。 还原区域30至少形成在半导体层23的沟道部分23c中，并且还原区域30具有比半导体层23的其余部分中诸如In的金属的单质更高的含量。

公开(公告)号：US08685803B2

公开(公告)日：2014-04-01

申请号：US13514081

申请日：2010-12-03

申请人： Yoshimasa Chikama ,  Hirohiko Nishiki ,  Yoshifumi Ohta ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Okifumi Nakagawa ,  Yoshiyuki Harumoto ,  Hinae Mizuno

发明人： Yoshimasa Chikama ,  Hirohiko Nishiki ,  Yoshifumi Ohta ,  Yuuji Mizuno ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Okifumi Nakagawa ,  Yoshiyuki Harumoto

IPC分类号： H01L21/00

CPC分类号： H01L27/1225 ,  G02F1/13458 ,  G02F1/136213 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248

摘要： A semiconductor device includes: a thin film transistor having a gate line (3a), a first insulating film (5), an island-shaped oxide semiconductor layer (7a), a second insulating film (9), a source line (13as), a drain electrode (13ad), and a passivation film; and a terminal portion having a first connecting portion (3c) made of the same conductive film as the gate line, a second connecting portion (13c) made of the same conductive film as the source line and the drain electrode, and a third connecting portion (19c) formed on the second connecting portion. The second connecting portion is in contact with the first connecting portion within a first opening (11c) provided in the first and second insulating films; the third connecting portion (19c) is in contact with the second connecting portion within a second opening (17c) provided in the passivation film; and the second connecting portion (13c) covers end faces of the first and second insulating films within the first opening (11c), but does not cover an end face of the passivation film (15) within the second opening (17c). As a result, the taper shape of a contact hole of the terminal portion can be controlled with a high precision.

摘要翻译： 半导体器件包括：具有栅极线（3a），第一绝缘膜（5），岛状氧化物半导体层（7a），第二绝缘膜（9），源极线（13as））的薄膜晶体管， ，漏电极（13ad）和钝化膜; 以及具有由与栅极线相同的导电膜制成的第一连接部分（3c）的端子部分，由与源极线和漏极电极相同的导电膜制成的第二连接部分（13c）和第三连接部分 （19c）形成在第二连接部分上。 第二连接部分在设置在第一和第二绝缘膜中的第一开口（11c）内与第一连接部分接触; 所述第三连接部分（19c）在设置在所述钝化膜中的第二开口（17c）内与所述第二连接部分接触; 并且所述第二连接部分（13c）覆盖所述第一开口（11c）内的所述第一绝缘膜和所述第二绝缘膜的端面，但不覆盖所述第二开口（17c）内的所述钝化膜（15）的端面。 结果，可以高精度地控制端子部分的接触孔的锥形形状。

公开(公告)号：US08530899B2

公开(公告)日：2013-09-10

申请号：US13518566

申请日：2010-12-21

申请人： Yoshiyuki Harumoto ,  Takeshi Hara ,  Tohru Okabe ,  Takeshi Yaneda ,  Tetsuya Aita ,  Tsuyoshi Inoue ,  Michiko Takei

发明人： Yoshiyuki Harumoto ,  Takeshi Hara ,  Tohru Okabe ,  Takeshi Yaneda ,  Tetsuya Aita ,  Tsuyoshi Inoue ,  Michiko Takei

IPC分类号： H01L29/04

CPC分类号： H01L29/786 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78678 ,  H01L29/78696 ,  H01L33/08

摘要： The present invention has an object of providing a TFT in which generation of an OFF current is reduced by an efficient manufacturing method. A thin film transistor 100 according to the present invention has a gate electrode 12 formed on a substrate 10, an insulating layer 14 formed on the gate electrode 12, a microcrystalline amorphous silicon layer 18 and an amorphous silicon layer 16 that are formed on the insulating layer 14, a semiconductor layer 20 containing an impurity formed on the amorphous silicon layer 16, and a source electrode 22A and a drain electrode 22B that are formed on the semiconductor layer 20 containing an impurity. The microcrystalline amorphous silicon layer 18 and the semiconductor layer 20 containing an impurity are connected to each other through the amorphous silicon layer 16 without being in direct contact with each other.

摘要翻译： 本发明的目的是提供一种通过有效的制造方法来减少OFF电流的产生的TFT。 根据本发明的薄膜晶体管100具有形成在基板10上的栅电极12，形成在栅电极12上的绝缘层14，形成在绝缘层上的微晶非晶硅层18和非晶硅层16。 层14，包含形成在非晶硅层16上的杂质的半导体层20以及形成在包含杂质的半导体层20上的源电极22A和漏极22B。 含有杂质的微晶非晶硅层18和半导体层20通过非晶硅层16彼此连接而不直接接触。

公开(公告)号：US20130175521A1

公开(公告)日：2013-07-11

申请号：US13701028

申请日：2011-05-23

申请人： Masao Moriguchi ,  Michiko Takei ,  Yohsuke Kanzaki ,  Tsuyoshi Inoue ,  Tetsuo Fukaya ,  Yudai Takanishi ,  Takatsugu Kusumi ,  Yoshiki Nakatani ,  Tetsuya Okamoto ,  Kenji Nakanishi

发明人： Masao Moriguchi ,  Michiko Takei ,  Yohsuke Kanzaki ,  Tsuyoshi Inoue ,  Tetsuo Fukaya ,  Yudai Takanishi ,  Takatsugu Kusumi ,  Yoshiki Nakatani ,  Tetsuya Okamoto ,  Kenji Nakanishi

IPC分类号： H01L29/786 ,  H01L29/24

CPC分类号： H01L29/7869 ,  H01L29/24 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78696

摘要： A TFT 20 includes a gate electrode 21, a gate insulating film 22, a semiconductor layer 23, a source electrode 24, a drain electrode 25, etc. The semiconductor layer 23 is comprised of a metal oxide semiconductor (IGZO), and has a source portion 23a that contacts the source electrode 24, a drain electrode 23b that contacts the drain electrode 25, and a channel portion 23c that is located between the source and drain portions 23a, 23b. A reduced region 30 is formed at least in the channel portion 23c of the semiconductor layer 23, and the reduced region 30 has a higher content of a simple substance of a metal such as In than the remaining portion of the semiconductor layer 23.

摘要翻译： TFT20包括栅极电极21，栅极绝缘膜22，半导体层23，源极24，漏极电极25等。半导体层23由金属氧化物半导体（IGZO）构成，具有 与源电极24接触的源部23a，与漏电极25接触的漏电极23b和位于源极部23a，第二漏极23b之间的沟道部23c。 还原区域30至少形成在半导体层23的沟道部分23c中，并且还原区域30具有比半导体层23的其余部分中诸如In的金属的单质更高的含量。

公开(公告)号：US20120241750A1

公开(公告)日：2012-09-27

申请号：US13514081

申请日：2010-12-03

申请人： Yoshimasa Chikama ,  Hirohiko Nishiki ,  Yoshifumi Ohta ,  Yuuji Mizuno ,  Hinae Mizuno ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Okifumi Nakagawa ,  Yoshiyuki Harumoto

发明人： Yoshimasa Chikama ,  Hirohiko Nishiki ,  Yoshifumi Ohta ,  Yuuji Mizuno ,  Hinae Mizuno ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Okifumi Nakagawa ,  Yoshiyuki Harumoto

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1225 ,  G02F1/13458 ,  G02F1/136213 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248

摘要： A semiconductor device includes: a thin film transistor having a gate line (3a), a first insulating film (5), an island-shaped oxide semiconductor layer (7a), a second insulating film (9), a source line (13as), a drain electrode (13ad), and a passivation film; and a terminal portion having a first connecting portion (3c) made of the same conductive film as the gate line, a second connecting portion (13c) made of the same conductive film as the source line and the drain electrode, and a third connecting portion (19c) formed on the second connecting portion. The second connecting portion is in contact with the first connecting portion within a first opening (11c) provided in the first and second insulating films; the third connecting portion (19c) is in contact with the second connecting portion within a second opening (17c) provided in the passivation film; and the second connecting portion (13c) covers end faces of the first and second insulating films within the first opening (11c), but does not cover an end face of the passivation film (15) within the second opening (17c). As a result, the taper shape of a contact hole of the terminal portion can be controlled with a high precision.

摘要翻译： 半导体器件包括：具有栅极线（3a），第一绝缘膜（5），岛状氧化物半导体层（7a），第二绝缘膜（9），源极线（13as））的薄膜晶体管， ，漏电极（13ad）和钝化膜; 以及具有由与栅极线相同的导电膜制成的第一连接部分（3c）的端子部分，由与源极线和漏极电极相同的导电膜制成的第二连接部分（13c）和第三连接部分 （19c）形成在第二连接部分上。 第二连接部分在设置在第一和第二绝缘膜中的第一开口（11c）内与第一连接部分接触; 所述第三连接部分（19c）在设置在所述钝化膜中的第二开口（17c）内与所述第二连接部分接触; 并且所述第二连接部分（13c）覆盖所述第一开口（11c）内的所述第一和第二绝缘膜的端面，但不覆盖所述第二开口（17c）内的所述钝化膜（15）的端面。 结果，可以高精度地控制端子部分的接触孔的锥形形状。