公开(公告)号：US07299022B2

公开(公告)日：2007-11-20

申请号：US10868810

申请日：2004-06-17

申请人： Takahiro Inoue ,  Noboru Takeuchi

发明人： Takahiro Inoue ,  Noboru Takeuchi

IPC分类号： H04B1/06 ,  H03D3/24

CPC分类号： H03G3/3084

摘要： A carrier detecting circuit which generates a carrier detection level by integral action based on a reception signal and detects using the carrier detection level whether a carrier exists is disclosed and includes an integration capacitor that is charged and discharged using a difference current between a current charged from a charging circuit and a current discharged to a discharging circuit, where the charging circuit and the discharging circuit are provided in an integrator which performs the integral action.

摘要翻译： 一种载波检测电路，其基于接收信号通过积分动作生成载波检测电平，并且使用载波检测电平检测载波是否存在，并且包括使用从 充电电路和放电到放电电路的电流，其中充电电路和放电电路设置在执行积分作用的积分器中。

公开(公告)号：US20070170578A1

公开(公告)日：2007-07-26

申请号：US11584518

申请日：2006-10-23

申请人： Noriyuki Yoshikawa ,  Noboru Takeuchi ,  Kenichi Itou ,  Toshiyuki Fukuda

发明人： Noriyuki Yoshikawa ,  Noboru Takeuchi ,  Kenichi Itou ,  Toshiyuki Fukuda

IPC分类号： H01L23/12

CPC分类号： H01L23/49811 ,  H01L21/4846 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/1423 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/113 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09509 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A semiconductor device has upper electrodes and external terminals which are protruding above the both surfaces of a substrate for semiconductor device and connected to each other by penetrating electrodes, a first insulating film covering at least a metal pattern except for the portions of the first insulating film corresponding to the upper electrodes, a second insulating film covering at least another metal pattern except for the portions of the second insulating film corresponding to the external terminals, and a semiconductor element connected to the upper electrodes and placed on the substrate for semiconductor device. The solder-connected surface of the external terminal is positioned to have a height larger than that of a surface of the second insulating film. The semiconductor element is placed on the first insulating film and covered, together with the upper electrodes, with a mold resin.

摘要翻译： 半导体器件具有上部电极和外部端子，该上部电极和外部端子突出在半导体器件用基板的两面之上，并且通过穿透电极彼此连接，除了第一绝缘膜的部分之外至少覆盖金属图案的第一绝缘膜 对应于上部电极的第二绝缘膜，覆盖除了与外部端子对应的第二绝缘膜的部分之外的至少另一种金属图案的第二绝缘膜，以及连接到上部电极并放置在半导体器件的基板上的半导体元件。 外部端子的焊接连接表面被定位成具有比第二绝缘膜的表面高的高度。 将半导体元件放置在第一绝缘膜上并与上部电极一起用模制树脂覆盖。

公开(公告)号：US20060273433A1

公开(公告)日：2006-12-07

申请号：US11474659

申请日：2006-06-26

申请人： Kenichi Itou ,  Noboru Takeuchi ,  Shigetoyo Kawakami ,  Toshiyuki Fukuda

发明人： Kenichi Itou ,  Noboru Takeuchi ,  Shigetoyo Kawakami ,  Toshiyuki Fukuda

IPC分类号： H01L23/495

CPC分类号： H01L21/568 ,  H01L21/4828 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48644 ,  H01L2224/49171 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/20752 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

公开(公告)号：US20060232900A1

公开(公告)日：2006-10-19

申请号：US11400364

申请日：2006-04-10

申请人： Noboru Takeuchi ,  Takahiro Inoue

发明人： Noboru Takeuchi ,  Takahiro Inoue

IPC分类号： H02H3/20

CPC分类号： H03K3/02337

摘要： A comparator circuit of the present invention includes a comparator section and a current buffer circuit. In a normal mode, a standby current outputted from the comparator section is amplified by a predetermined times at the current buffer circuit. On the other hand, the standby current is not amplified in a standby mode.

公开(公告)号：US20050093118A1

公开(公告)日：2005-05-05

申请号：US10996783

申请日：2004-11-24

申请人： Kenichi Itou ,  Noboru Takeuchi ,  Shigetoyo Kawakami ,  Toshiyuki Fukuda

发明人： Kenichi Itou ,  Noboru Takeuchi ,  Shigetoyo Kawakami ,  Toshiyuki Fukuda

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L31/0328

CPC分类号： H01L21/568 ,  H01L21/4828 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48644 ,  H01L2224/49171 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/20752 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

公开(公告)号：US20050035399A1

公开(公告)日：2005-02-17

申请号：US10912751

申请日：2004-08-04

申请人： Fujio Masuoka ,  Shinji Horii ,  Takuji Tanigami ,  Takashi Yokoyama ,  Noboru Takeuchi

发明人： Fujio Masuoka ,  Shinji Horii ,  Takuji Tanigami ,  Takashi Yokoyama ,  Noboru Takeuchi

IPC分类号： H01L27/108 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/26586 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7828 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78696

摘要： A semiconductor device comprising a memory cell which includes: a pillar-shaped semiconductor layer of a first conductive type formed on a semiconductor substrate; source and drain diffusion layers of a second conductive type formed in upper and lower portions of the pillar-shaped semiconductor layer; a semiconductor layer of the second conductive type or a cavity formed inside the pillar-shaped semiconductor layer; and a gate electrode formed on a side face of the pillar-shaped semiconductor layer via a gate insulating film, or a control gate electrode formed on the side face of the pillar-shaped semiconductor layer via a charge accumulation layer.

摘要翻译： 一种半导体器件，包括存储单元，其包括：形成在半导体衬底上的第一导电类型的柱状半导体层; 在柱状半导体层的上部和下部形成的第二导电类型的源极和漏极扩散层; 第二导电类型的半导体层或形成在柱状半导体层内部的空腔; 以及经由栅极绝缘膜形成在柱状半导体层的侧面上的栅电极，或者经由电荷累积层形成在柱状半导体层的侧面上的控制栅电极。

公开(公告)号：US20050003786A1

公开(公告)日：2005-01-06

申请号：US10868810

申请日：2004-06-17

申请人： Takahiro Inoue ,  Noboru Takeuchi

发明人： Takahiro Inoue ,  Noboru Takeuchi

IPC分类号： H03D1/10 ,  H03G3/30 ,  H04L27/06 ,  H04B1/06 ,  H04B1/16 ,  H04B7/00

CPC分类号： H03G3/3084

摘要： A conventional carrier detecting circuit which generates a carrier detection level by integral action based on a reception signal and detects using the carrier detection level whether a carrier exists is arranged to charge and discharge in the following manner, an integration capacitor in an integrator that performs the integral action. Namely, the integration capacitor is (i) either charged or discharged in accordance with a result of the discrimination of the reception signal at the carrier detection level, or (ii) charged in accordance with the result of the discrimination while the integration capacitor is constantly discharged at a constant level. In contrast, a carrier detecting circuit of the present invention is arranged so that the integration capacitor is both charged and discharged constantly at a level that varies in accordance with the result of the discrimination. In other words, the integration capacitor is charged and discharged using a difference current between a current charged from a charging circuit and a current discharged to a discharging circuit. With this, it is possible to reduce the chip area without causing problems due to the reduction of the currents flowing through the transistors.

摘要翻译： 通过基于接收信号的积分动作生成载波检测电平的传统载波检测电路，并且使用载波检测电平检测是否存在载波被布置为以下列方式对放电进行充放电：积分器中的积分电容器执行 积分行动。 也就是说，积分电容器是（i）根据载波检测电平的接收信号的鉴别结果进行充电或放电，或者（ii）在积分电容器不断地根据判别结果进行充电的情况下 以恒定水平排放。 相反，本发明的载波检测电路被布置成使得积分电容器被以恒定的方式被充放电，其电平根据鉴别结果而变化。 换句话说，使用从充电电路充电的电流与放电电路放电的电流之间的差电流对积分电容器进行充放电。 由此，可以减少芯片面积而不会由于流过晶体管的电流的减少而引起问题。