公开(公告)号：US5825694A

公开(公告)日：1998-10-20

申请号：US807007

申请日：1997-02-26

申请人： Hiromi Okimoto ,  Masanori Hayashikoshi ,  Youichi Tobita

发明人： Hiromi Okimoto ,  Masanori Hayashikoshi ,  Youichi Tobita

IPC分类号： G06F11/20 ,  G11C8/08 ,  G11C8/10 ,  G11C29/00 ,  G11C7/00

CPC分类号： G06F11/2007 ,  G11C29/70 ,  G11C29/78 ,  G11C29/832 ,  G11C8/08 ,  G11C8/10

摘要： A column select line includes a first layer column select line and a second layer column select line formed above the first layer column select line and connected thereto at any point. Furthermore, clamping circuits each for clamping each word line of paired main word lines at a constant potential are provided in a semiconductor memory device having main and secondary word line structure. With such a structure, malfunction due to multiselection of memory cells can be avoided even when the column select line or the paired main word lines is disconnected.

公开(公告)号：US5815446A

公开(公告)日：1998-09-29

申请号：US763120

申请日：1996-12-10

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： H01L21/8234 ,  G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  G11C11/409 ,  H01L27/06 ,  H03H11/24 ,  H03K17/06 ,  H03K17/22 ,  H03K19/0948 ,  G11C11/40

CPC分类号： G05F1/465 ,  G05F3/247 ,  G11C5/145 ,  G11C5/146 ,  H03H11/245 ,  H03K17/063

摘要： A potential generating circuit includes at least a pair of MOS transistors each of which is diode-connected and series connected between an output node and a given potential node and disposed in same forward direction. Each MOS transistor has its back gate and a gate interconnected. A capacitor is coupled between a connection node of the pair of MOS transistors and an input node to which an alternating signal is inputted.

摘要翻译： 电位发生电路至少包括一对MOS晶体管，每个MOS晶体管二极管连接在一起，串联连接在输出节点和给定的电位节点之间并且以相同的正向方向布置。 每个MOS晶体管都有其背栅极和互连的栅极。 电容器耦合在一对MOS晶体管的连接节点和输入交替信号的输入节点之间。

公开(公告)号：US5726941A

公开(公告)日：1998-03-10

申请号：US762903

申请日：1996-12-10

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： H01L21/8234 ,  G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  G11C11/409 ,  H01L27/06 ,  H03H11/24 ,  H03K17/06 ,  H03K17/22 ,  H03K19/0948 ,  G11C13/00

CPC分类号： G05F1/465 ,  G05F3/247 ,  G11C5/145 ,  G11C5/146 ,  H03H11/245 ,  H03K17/063

摘要： A power-on reset circuit for generating a power-on reset signal includes a capacitor which is charged in response to the application of an external power supply potential to an internal circuit. The capacitor is discharged through a diode-connected MOS transistor having its back gate and gate connected together, to prevent malfunction of the POR circuit when the external power supply potential is reapplied.

摘要翻译： 用于产生上电复位信号的上电复位电路包括响应于向内部电路施加外部电源电位而被充电的电容器。 电容器通过其背栅极和栅极连接在一起的二极管连接的MOS晶体管放电，以防止外部电源电位重新施加时POR电路的故障。

公开(公告)号：US4961007A

公开(公告)日：1990-10-02

申请号：US337218

申请日：1989-04-12

申请人： Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Youichi Tobita

发明人： Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Youichi Tobita

IPC分类号： G11C11/408 ,  G05F3/20 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： G05F3/205 ,  H02M3/07

摘要： A substrate bias potential generator for biasing a semiconductor substrate to a predetermined potential includes first and second substrate bias generating circuits which operate alternatively according to the potential of the substrate, whereby consumption of power in the substrate bias potential generator is reduced. The alternative operation of the bias generating circuits each activated by a pulse signal train is performed by using a first insulated gate transistor having a gate electrode connected to the semiconductor substrate, a second insulated gate transistor having a gate electrode for receiving the reference potential, an amplifier for differentially amplifying outputs of the first and second insulated gate transistors, an insulated gate transistor for charging an output of the amplifier to a predetermined potential when the amplifier is activated, and a circuit for transmitting the output of the differential amplifier to the first and second bias potential generating circuits. The differential amplifier is activated in response to an activation signal of a pulse train whereby an activation signal corresponding to the pulse train is transmitted to either substrate bias potential generating circuit.

摘要翻译： 用于将半导体衬底偏置到预定电位的衬底偏置电位发生器包括根据衬底的电位交替地操作的第一和第二衬底偏置产生电路，由此降低衬底偏置电位发生器中的功率消耗。 通过使用具有连接到半导体衬底的栅电极的第一绝缘栅极晶体管，具有用于接收参考电位的栅电极的第二绝缘栅极晶体管，执行由脉冲信号列激活的偏置产生电路的替代操作， 放大器，用于差分放大第一和第二绝缘栅极晶体管的输出;绝缘栅极晶体管，用于在放大器被激活时将放大器的输出充电到预定电位;以及电路，用于将差分放大器的输出传输到第一和第二绝缘栅极晶体管， 第二偏置电位发生电路。 差分放大器响应于脉冲串的激活信号被激活，由此将对应于脉冲串的激活信号传输到任一衬底偏置电位产生电路。

公开(公告)号：US4860259A

公开(公告)日：1989-08-22

申请号：US278374

申请日：1988-12-01

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： H01L27/10 ,  G11C11/40 ,  G11C29/34

CPC分类号： G11C29/34

摘要： In a semiconductor memory device comprising a plurality of memory cells, a test request detection circuit responds to a voltage, on an input terminal, higher than a range of voltages supplied under ordinary operation condition for producing a test signal. Responsive to the test signal, data which has been supplied to the semiconductor memory device are simultaneously written into a plurality of memory cells, and data are simultaneously read from a plurality of memory cells, and judgement is made as to whether or not the data from the memory cells coincide with the data originally supplied to the semiconductor memory device.

摘要翻译： 在包括多个存储单元的半导体存储器件中，测试请求检测电路响应于输入端子上的电压高于在正常操作条件下提供的用于产生测试信号的电压范围。 响应于测试信号，已经提供给半导体存储器件的数据被同时写入多个存储器单元，并且从多个存储器单元同时读取数据，并且判断数据是否来自 存储单元与最初提供给半导体存储器件的数据重合。

公开(公告)号：US4806788A

公开(公告)日：1989-02-21

申请号：US70254

申请日：1987-07-06

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： H01L27/04 ,  G05F1/46 ,  G05F3/24 ,  H01L21/66 ,  H01L21/70 ,  H01L21/822 ,  H03K17/687

CPC分类号： G05F3/24 ,  G05F1/465 ,  H01L2924/0002

摘要： A semiconductor integrated circuit is provided with an internal voltage generator to normally operate with internal source voltage which is lower than externally supplied source voltage and serves as operating source voltage. The semiconductor integrated circuit is further provided with a control circuit for controlling an internal source voltage generator so that voltage generated by the internal source voltage generator in burn-in or the like serves as first voltage which is higher than normal internal source voltage to accelerate the burn-in.

摘要翻译： 半导体集成电路具有内部电压发生器，以正常工作，其内部源极电压低于外部提供的电源电压并用作工作电源电压。 半导体集成电路还具有用于控制内部源电压发生器的控制电路，使得内部源电压发生器在老化等中产生的电压用作高于正常内部源极电压的第一电压，以加速 老化

公开(公告)号：US4695746A

公开(公告)日：1987-09-22

申请号：US763588

申请日：1985-08-08

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： H01L27/04 ,  G05F3/20 ,  G11C11/4074 ,  G11C11/408 ,  H01L21/822 ,  H01L27/10 ,  H03K3/354 ,  H03L1/00

CPC分类号： G11C11/4074 ,  G05F3/205

摘要： A substrate potential generating circuit for a semiconductor integrated circuit in which, in addition to a conventional circuit for supplying a bias current to the substrate, at least two additional bias current supplying circuits are provided. With this configuration, when the substrate potential reaches its final level, the substrate bias current from the conventional circuit is interrupted to reduce the power consumption of the integrated circuit.

摘要翻译： 一种用于半导体集成电路的衬底电位产生电路，其中除了用于向衬底提供偏置电流的常规电路之外，还提供了至少两个额外的偏置电流供应电路。 利用这种配置，当衬底电位达到其最终电平时，来自常规电路的衬底偏置电流被中断，以降低集成电路的功耗。

公开(公告)号：US4571509A

公开(公告)日：1986-02-18

申请号：US525901

申请日：1983-08-24

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/09425

摘要： An output circuit for a semiconductor integrated circuit is improved by reverse biasing the gates of non-selected output field effect transistors (MOSTs). A control MOST, when actuated by a chip-select signal, connects the gate of its associated output MOST with a negative voltage so that the non-selected output MOSTs are completely cut off. The invention avoids the problem which arises with the use of very short channel output MOSTs such that the channel cannot be completely cut off if a zero bias is applied to the gate.

摘要翻译： 通过反向偏置未选择的输出场效应晶体管（MOST）的栅极来提高半导体集成电路的输出电路。 控制MOST当由芯片选择信号驱动时，将其相关输出MOST的栅极与负电压连接，使得未选择的输出MOST被完全切断。 本发明避免了使用非常短的通道输出MOST引起的问题，使得如果向门施加零偏压，则不能完全切断通道。

公开(公告)号：US08571170B2

公开(公告)日：2013-10-29

申请号：US13718438

申请日：2012-12-18

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G11C19/00

CPC分类号： G11C19/287 ,  G09G2310/0286 ,  G09G2320/0252 ,  G11C19/28

摘要： An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).

公开(公告)号：US08462098B2

公开(公告)日：2013-06-11

申请号：US12705235

申请日：2010-02-12

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/3677 ,  G09G2310/0267 ,  G11C19/28 ,  G11C27/04 ,  H01L29/78666 ,  H01L29/7869 ,  H01L29/94

摘要： An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver.

摘要翻译： 电光装置能够有效地使用栅极线驱动电路的区域，并且防止栅极线选择信号的上升速度降低（上升延迟），移位寄存器电路由单导电型 适用于器件的晶体管。 栅极线驱动电路包括用于驱动多条栅极线的奇数行的奇数驱动器，以及用于驱动其偶数行的偶数驱动器。 奇数和偶数驱动器中的每个单元移位寄存器在第二个上一行接收选择信号，并在两个水平周期之后激活其自己的选择信号。 偶数驱动器的起始脉冲相对于奇数驱动器的起始脉冲被相位延迟一个水平周期。