利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

54 条记录 (耗时 0.04 秒)

    Phase Change Memory Device and Method of Forming the Same
    41.
    发明申请
    Phase Change Memory Device and Method of Forming the Same 有权
    相变存储器件及其形成方法

    公开(公告)号：US20080116437A1

    公开(公告)日：2008-05-22

    申请号：US11769532

    申请日：2007-06-27

    申请人： Gyu-Hwan Oh ,  In-Sun Park ,  Hyun-Seok Lim ,  Ki-Jong Lee ,  Nak-Hyun Lim

    发明人： Gyu-Hwan Oh ,  In-Sun Park ,  Hyun-Seok Lim ,  Ki-Jong Lee ,  Nak-Hyun Lim

    IPC分类号： H01L47/00

    CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    摘要： A phase change memory device includes a current restrictive element interposed between an electrically conductive element and a phase change material. The current restrictive element includes a plurality of overlapping film patterns, each of which having a respective first portion proximal to the conductive element and a second portion proximal to the phase change material. The second portions are configured and dimensioned to have higher resistance than the first portions.

    摘要翻译： 相变存储器件包括介于导电元件和相变材料之间的电流限制元件。 电流限制元件包括多个重叠的膜图案，每个重叠的膜图案具有靠近导电元件的相应的第一部分和靠近相变材料的第二部分。 第二部分的构造和尺寸设计成具有比第一部分更高的电阻。

    Method for forming a metal silicide layer in a semiconductor device
    42.
    发明申请
    Method for forming a metal silicide layer in a semiconductor device 有权

    公开(公告)号：US20060068585A1

    公开(公告)日：2006-03-30

    申请号：US11280425

    申请日：2005-11-16

    申请人： Eung-Joon Lee ,  In-Sun Park ,  Kwan-Jong Roh

    发明人： Eung-Joon Lee ,  In-Sun Park ,  Kwan-Jong Roh

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/6653 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665

    摘要： On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.

    Semiconductor device having a metal silicide layer and method for manufacturing the same
    43.
    发明授权
    Semiconductor device having a metal silicide layer and method for manufacturing the same 有权
    具有金属硅化物层的半导体器件及其制造方法

    公开(公告)号：US06740587B2

    公开(公告)日：2004-05-25

    申请号：US09949853

    申请日：2001-09-12

    申请人： Won-Sang Song ,  Jeong-Hwan Yang ,  In-Sun Park ,  Byoung-Moon Yoon

    发明人： Won-Sang Song ,  Jeong-Hwan Yang ,  In-Sun Park ,  Byoung-Moon Yoon

    IPC分类号： H01L2144

    CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a semiconductor device having a metal suicide layer and a method for forming the metal silicide layer, the semiconductor device having a metal silicide-semiconductor contact structure, wherein the semiconductor device includes a substrate, an insulation layer with an opening, in which a metal silicide layer is formed using a native metal silicide with a first phase and a second phase, upon which a conductive layer is formed. The second phase has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. A reaction between the metal silicide layer of the first phase and the silicon results in the metal silicide layer of the second phase having high phase stability and low resistance.

    摘要翻译： 本发明提供一种具有金属硅化物层的半导体器件和用于形成金属硅化物层的方法，该半导体器件具有金属硅化物半导体接触结构，其中半导体器件包括衬底，具有开口的绝缘层， 使用具有第一相和第二相的天然金属硅化物形成金属硅化物层，在其上形成导电层。 第二相具有与第一相的第二化学计量组成比不同的第一化学计量组成比。 第一相的金属硅化物层与硅之间的反应导致第二相的金属硅化物层具有高相稳定性和低电阻。

    Non-Volatile Memory Devices Having Resistance Changeable Elements And Related Systems And Methods
    48.
    发明申请
    Non-Volatile Memory Devices Having Resistance Changeable Elements And Related Systems And Methods 有权
    具有电阻可变元件和相关系统和方法的非易失性存储器件

    公开(公告)号：US20120112156A1

    公开(公告)日：2012-05-10

    申请号：US13220777

    申请日：2011-08-30

    申请人： Heung-Kyu Park ,  In-Sun Park ,  In-Gyu Baek ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Woo-Bin Song

    发明人： Heung-Kyu Park ,  In-Sun Park ,  In-Gyu Baek ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Woo-Bin Song

    IPC分类号： H01L45/00

    CPC分类号： H01L27/1021 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

    摘要： A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.

    摘要翻译： 非易失性存储器件可以包括衬底上的第一字线，第一字线上的绝缘层和绝缘层上的第二字线，使得绝缘层在第一和第二字线之间。 位柱可以在相对于衬底的表面垂直的方向上相邻于第一字线，绝缘层和第二字线延伸，并且位柱可以是导电的。 此外，第一存储单元可以包括电耦合在第一字线和位柱之间的第一电阻可变元件，并且第二存储单元可以包括电耦合在第二字线和位柱之间的第二电阻可变元件。 还讨论了相关方法和系统。