公开(公告)号：US20050255663A1

公开(公告)日：2005-11-17

申请号：US10856868

申请日：2004-06-01

申请人： Katsuaki Natori ,  Koji Yamakawa ,  Hiroyuki Kanaya ,  Karl Hornik ,  Andreas Hiliger

发明人： Katsuaki Natori ,  Koji Yamakawa ,  Hiroyuki Kanaya ,  Karl Hornik ,  Andreas Hiliger

IPC分类号： H01L27/105 ,  H01L21/20 ,  H01L21/8246 ,  H01L27/115

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A semiconductor device according to the present invention comprises a capacitor including a lower electrode, a dielectric material, and an upper electrode. The device further comprises a first protective film which contacts the upper electrode to constitute a columnar structure of films formed by a sputtering process and a second protective film formed above the first protective film by a CVD process.

摘要翻译： 根据本发明的半导体器件包括包括下电极，电介质材料和上电极的电容器。 该装置还包括与上电极接触以构成通过溅射工艺形成的膜的柱状结构的第一保护膜和通过CVD工艺形成在第一保护膜上方的第二保护膜。

公开(公告)号：US20050205910A1

公开(公告)日：2005-09-22

申请号：US10960029

申请日：2004-10-08

申请人： Yoshinori Kumura ,  Hiroyuki Kanaya ,  Tohru Ozaki

发明人： Yoshinori Kumura ,  Hiroyuki Kanaya ,  Tohru Ozaki

IPC分类号： H01L27/105 ,  H01L21/00 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A transistor including a source/drain region is formed on a semiconductor substrate. A plug electrode is formed on the source/drain region. A conductive film is formed on the plug electrode. A first insulation film is formed on the conductive film. A lower electrode is formed on the first insulation film, and electrically connected to the conductive film formed on the plug electrode. A ferroelectric film is formed on the lower electrode. An upper electrode is formed on the ferroelectric film.

摘要翻译： 包括源极/漏极区域的晶体管形成在半导体衬底上。 插头电极形成在源极/漏极区域上。 在插头电极上形成导电膜。 在导电膜上形成第一绝缘膜。 在第一绝缘膜上形成下电极，与形成在插塞电极上的导电膜电连接。 在下电极上形成铁电体膜。 在铁电体膜上形成上部电极。

公开(公告)号：US20050186767A1

公开(公告)日：2005-08-25

申请号：US11110933

申请日：2005-04-21

申请人： Katsuaki Natori ,  Keisuke Nakazawa ,  Koji Yamakawa ,  Hiroyuki Kanaya ,  Yoshinori Kumura ,  Hiroshi Itokawa ,  Osamu Arisumi

发明人： Katsuaki Natori ,  Keisuke Nakazawa ,  Koji Yamakawa ,  Hiroyuki Kanaya ,  Yoshinori Kumura ,  Hiroshi Itokawa ,  Osamu Arisumi

IPC分类号： H01L21/28 ,  C23C14/08 ,  C23C14/58 ,  C23C16/00 ,  H01L21/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/26 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8246 ,  H01L23/58 ,  H01L27/105 ,  H01L27/115 ,  H01L29/417 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L27/11502 ,  C23C14/08 ,  C23C14/5806 ,  H01L21/67115 ,  H01L27/11507 ,  H01L28/65

摘要： An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.

摘要翻译： 公开了一种用于制造半导体器件的装置，其包括容纳待处理基板的室，该基板具有含有至少一种将成为挥发性金属化合物的成分的金属元素的膜，加热基板 保持在所述室中的吸附剂和设置在所述室中并通过加热所述基板吸附由所述膜产生的挥发性金属化合物的吸附剂。

公开(公告)号：US20050128663A1

公开(公告)日：2005-06-16

申请号：US10750814

申请日：2004-01-05

申请人： Soichi Yamazaki ,  Hiroyuki Kanaya ,  Kazuhiro Tomioka ,  Koji Yamakawa

发明人： Soichi Yamazaki ,  Hiroyuki Kanaya ,  Kazuhiro Tomioka ,  Koji Yamakawa

IPC分类号： H01L27/105 ,  H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H02H9/00

CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

摘要： There is disclosed a semiconductor device comprising a capacitor comprising a lower electrode provided above a substrate, a capacitor insulating film selectively provided on the lower electrode, and an upper electrode selectively provided above the lower electrode so that the capacitor insulating film can be interposed between the upper and lower electrodes, an electrode protection film formed of oxide conductors containing at least one of metal elements such as Sr, Ti, Ru, Ir and Pt, and provided on the upper electrode, an interlayer insulating film provided on the electrode protection film, an upper layer interconnect wire for the lower electrode provided on the interlayer insulating film, and electrically connected to the lower electrode, and an upper layer interconnect wire for the upper electrode provided on the interlayer insulating film, and electrically connected to the upper electrode.

摘要翻译： 公开了一种半导体器件，其包括电容器，该电容器包括设置在基板上的下电极，选择性地设置在下电极上的电容器绝缘膜，以及选择性地设置在下电极上方的上电极，使得电容器绝缘膜可以介于 上下电极，由包含Sr，Ti，Ru，Ir和Pt等金属元素中的至少一种的氧化物导体形成的电极保护膜，设置在上部电极上，设置在电极保护膜上的层间绝缘膜， 用于下层电极的上层互连线设置在层间绝缘膜上并电连接到下电极，以及上层电介质线，用于上电极，设置在层间绝缘膜上，并电连接到上电极。

公开(公告)号：US06855565B2

公开(公告)日：2005-02-15

申请号：US10706970

申请日：2003-11-14

申请人： Hiroyuki Kanaya ,  Andreas Hilliger

发明人： Hiroyuki Kanaya ,  Andreas Hilliger

IPC分类号： H01L21/00 ,  H01L21/8246 ,  H01L27/115 ,  H01L31/119

CPC分类号： H01L27/11507 ,  H01L27/11502

摘要： First and second semiconductor regions are formed separately from each other in a semiconductor substrate. A gate electrode is formed above the semiconductor substrate which lies between the first and second semiconductor regions. An interlayer insulating film is formed on the semiconductor substrate to cover the first and second semiconductor regions and the gate electrode. First and second lower electrodes are formed on the interlayer insulating film. A first contact plug is formed in the interlayer insulating film in contact with the first lower electrode. A second contact plug is formed in the interlayer insulating film in contact with the second lower electrode. A first ferroelectric film is formed on the first lower electrode. A first upper electrode is formed on the first ferroelectric film. A second ferroelectric film is formed on the second lower electrode. A second upper electrode is formed on the second ferroelectric film.

摘要翻译： 第一和第二半导体区域在半导体衬底中彼此分开地形成。 在位于第一和第二半导体区域之间的半导体衬底的上方形成栅电极。 在半导体衬底上形成层间绝缘膜以覆盖第一和第二半导体区域和栅电极。 第一和第二下电极形成在层间绝缘膜上。 在与第一下电极接触的层间绝缘膜中形成第一接触插塞。 在与第二下电极接触的层间绝缘膜中形成第二接触插塞。 第一铁电体膜形成在第一下部电极上。 第一上电极形成在第一铁电体膜上。 在第二下部电极上形成第二铁电体膜。 第二上电极形成在第二铁电体膜上。

公开(公告)号：US06511877B2

公开(公告)日：2003-01-28

申请号：US09922074

申请日：2001-08-06

申请人： Hiroyuki Kanaya ,  Osamu Hidaka ,  Kumi Okuwada ,  Hiroshi Mochizuki

发明人： Hiroyuki Kanaya ,  Osamu Hidaka ,  Kumi Okuwada ,  Hiroshi Mochizuki

IPC分类号： H01L218242

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a fist hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.

公开(公告)号：US5990507A

公开(公告)日：1999-11-23

申请号：US889470

申请日：1997-07-08

申请人： Hiroshi Mochizuki ,  Kumi Okuwada ,  Hiroyuki Kanaya ,  Osamu Hidaka ,  Susumu Shuto ,  Iwao Kunishima

发明人： Hiroshi Mochizuki ,  Kumi Okuwada ,  Hiroyuki Kanaya ,  Osamu Hidaka ,  Susumu Shuto ,  Iwao Kunishima

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11507 ,  H01L21/76895 ,  H01L27/10852 ,  H01L27/11502 ,  H01L28/55

摘要： A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底的表面上形成包括漏区和源区的MIS晶体管，所述漏极区和源区各自由杂质扩散区形成，在所述半导体衬底之后形成绝缘膜 MIS晶体管已经形成，在绝缘膜中选择性地形成接触孔，将接触孔埋入电容器接触插塞中，该电容器接触插塞的下端与MIS晶体管的漏极区域和源极区域中的一个接触，形成 在形成电容器接触插塞之后，在绝缘膜上形成具有下电极，铁电体膜和上电极的铁电电容器，并且形成用于建立铁电电容器的上电极和上电极之间的连接的电线 电容器接触插头。

公开(公告)号：US09105572B2

公开(公告)日：2015-08-11

申请号：US14203400

申请日：2014-03-10

申请人： Hiroyuki Kanaya ,  Dong Jun Kim ,  Sung Hoon Lee

发明人： Hiroyuki Kanaya ,  Dong Jun Kim ,  Sung Hoon Lee

IPC分类号： H01L27/00 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  G11C7/18

CPC分类号： H01L27/228 ,  G11C7/18 ,  G11C11/16 ,  G11C11/161 ,  H01L27/222 ,  H01L43/12

摘要： According to one embodiment, a magnetic memory includes a cell transistor including a first source/drain diffusion layer and a second source/drain diffusion layer, a first contact on the first source/drain diffusion layer, a memory element on the first contact, and a second contact on the second source/drain diffusion layer, the second contact including a first plug on the second source/drain diffusion layer, and a second plug on the first plug.

摘要翻译： 根据一个实施例，磁存储器包括单元晶体管，其包括第一源极/漏极扩散层和第二源极/漏极扩散层，第一源极/漏极扩散层上的第一触点，第一触点上的存储元件，以及 在第二源/漏扩散层上的第二触点，第二触点包括在第二源极/漏极扩散层上的第一插头和第一插头上的第二插头。

公开(公告)号：US08592928B2

公开(公告)日：2013-11-26

申请号：US13237586

申请日：2011-09-20

申请人： Keiji Hosotani ,  Hiroyuki Kanaya ,  Takeshi Kajiyama

发明人： Keiji Hosotani ,  Hiroyuki Kanaya ,  Takeshi Kajiyama

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： According to one embodiment, a magnetic random access memory includes a selection element formed on a semiconductor substrate, an interlayer dielectric film formed above the selection element, a contact layer formed in the interlayer dielectric film, and electrically connected to the selection element, a lower electrode layer made of a metal material, and electrically connected to the contact layer, a metal oxide insulating film made of an oxide of the metal material, and surrounding a side surface of the lower electrode layer, a magnetoresistive element formed on the lower electrode layer, an upper electrode layer formed on the magnetoresistive element, a sidewall insulating film formed on a side surface of the magnetoresistive element and a side surface of the upper electrode layer, and a bit line electrically connected to the upper electrode layer.

摘要翻译： 根据一个实施例，磁性随机存取存储器包括形成在半导体衬底上的选择元件，形成在选择元件上方的层间电介质膜，形成于层间电介质膜中的电连接到选择元件的接触层， 电极层，与金属材料电连接，由金属材料的氧化物构成的金属氧化物绝缘膜，围绕下部电极层的侧面，形成在下部电极层上的磁阻元件 形成在磁阻元件上的上电极层，形成在磁阻元件的侧面上的侧壁绝缘膜和上电极层的侧面，以及与上电极层电连接的位线。

公开(公告)号：US20120068286A1

公开(公告)日：2012-03-22

申请号：US13237586

申请日：2011-09-20

申请人： Keiji Hosotani ,  Hiroyuki Kanaya ,  Takeshi Kajiyama

发明人： Keiji Hosotani ,  Hiroyuki Kanaya ,  Takeshi Kajiyama

IPC分类号： H01L29/82 ,  H01L21/20

CPC分类号： H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： According to one embodiment, a magnetic random access memory includes a selection element formed on a semiconductor substrate, an interlayer dielectric film formed above the selection element, a contact layer formed in the interlayer dielectric film, and electrically connected to the selection element, a lower electrode layer made of a metal material, and electrically connected to the contact layer, a metal oxide insulating film made of an oxide of the metal material, and surrounding a side surface of the lower electrode layer, a magnetoresistive element formed on the lower electrode layer, an upper electrode layer formed on the magnetoresistive element, a sidewall insulating film formed on a side surface of the magnetoresistive element and a side surface of the upper electrode layer, and a bit line electrically connected to the upper electrode layer.

摘要翻译： 根据一个实施例，磁性随机存取存储器包括形成在半导体衬底上的选择元件，形成在选择元件上方的层间电介质膜，形成于层间电介质膜中的电连接到选择元件的接触层， 电极层，与金属材料电连接，由金属材料的氧化物构成的金属氧化物绝缘膜，围绕下部电极层的侧面，形成在下部电极层上的磁阻元件 形成在磁阻元件上的上电极层，形成在磁阻元件的侧面上的侧壁绝缘膜和上电极层的侧面，以及与上电极层电连接的位线。