公开(公告)号：US08904326B2

公开(公告)日：2014-12-02

申请号：US13539258

申请日：2012-06-29

申请人： Mu-Jen Huang ,  Chih Chi Hsiao ,  Wei-Ting Lin ,  Tsung-Hsin Yu ,  Chien-Wen Chen ,  Yung-Chow Peng

发明人： Mu-Jen Huang ,  Chih Chi Hsiao ,  Wei-Ting Lin ,  Tsung-Hsin Yu ,  Chien-Wen Chen ,  Yung-Chow Peng

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.

摘要翻译： 在由至少一个处理器执行的半导体器件设计方法中，所述至少一个处理器提取半导体器件的布局中的至少一个电气部件的位置数据。 由至少一个处理器提取与所述至少一个电气部件相关联并且基于所述半导体器件的操作的模拟的电压数据。 基于所提取的位置数据，所提取的电压数据由所述至少一个处理器并入所述布局中以生成所述半导体器件的修改的布局。

公开(公告)号：US08850379B2

公开(公告)日：2014-09-30

申请号：US13352738

申请日：2012-01-18

申请人： Chien-Hung Chen ,  Yung-Chow Peng ,  Chung-Hui Chen ,  Chih Ming Yang

发明人： Chien-Hung Chen ,  Yung-Chow Peng ,  Chung-Hui Chen ,  Chih Ming Yang

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/08 ,  G06F2217/12 ,  H01L27/0207 ,  H01L29/94

摘要： A method of generating an optimized layout of semiconductor components in conformance with a set of design rules includes generating, for a unit cell including one or more semiconductor components, a plurality of configurations each of which satisfies some, but not all, of the design rules. For each configuration, it is checked whether a layout, which is a repeating pattern of the unit cell, satisfies the remaining design rules. Among the configurations which satisfy all of the design rules, the configuration providing an optimal value of a property is selected for generating the optimized layout of the semiconductor components.

摘要翻译： 根据一组设计规则生成半导体部件的优化布局的方法包括为包括一个或多个半导体部件的单元单元生成多个配置，每个配置满足设计规则的一些但不是全部 。 对于每个配置，检查作为单位单元的重复图案的布局是否满足剩余的设计规则。 在满足所有设计规则的配置中，选择提供最佳的属性值的配置用于生成半导体部件的优化布局。

公开(公告)号：US08648779B2

公开(公告)日：2014-02-11

申请号：US12582107

申请日：2009-10-20

申请人： Fu-Lung Hsueh ,  Yung-Chow Peng ,  Kuo-Liang Deng

发明人： Fu-Lung Hsueh ,  Yung-Chow Peng ,  Kuo-Liang Deng

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2320/02 ,  G09G2330/021

摘要： A method includes outputting a first signal from a first DAC decoder circuit in response to receiving a first number of bits of a digital control signal, outputting a second signal from a second DAC decoder circuit in response to receiving a second number of bits of the digital control signal, and alternately outputting one of the first and second signals to an LCD column from a buffer coupled to the first and second DAC decoder circuits. The first signal has a voltage level equal to one of a first plurality of voltage levels received at one of a first plurality of inputs of the first DAC decoder circuit. The second signal has a voltage level equal to one of a second plurality of voltage levels received at one of a second plurality of inputs of the second DAC decoder circuit.

摘要翻译： 一种方法包括响应于接收数字控制信号的第一位数而输出来自第一DAC解码器电路的第一信号，响应于接收到数字控制信号的第二位数而从第二DAC解码器电路输出第二信号 并且从耦合到第一和第二DAC解码器电路的缓冲器交替地将第一和第二信号之一输出到LCD列。 第一信号具有等于在第一DAC解码器电路的第一多个输入端之一处接收的第一多个电压电平之一的电压电平。 第二信号具有等于在第二DAC解码器电路的第二多个输入端之一处接收的第二多个电压电平之一的电压电平。

公开(公告)号：US20140040836A1

公开(公告)日：2014-02-06

申请号：US13562638

申请日：2012-07-31

申请人： Wen-Shen Chou ,  Yung-Chow Peng ,  Chih-Chiang Chang ,  Chin-Hua Wen

发明人： Wen-Shen Chou ,  Yung-Chow Peng ,  Chih-Chiang Chang ,  Chin-Hua Wen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.

摘要翻译： 除此之外，本文提供了用于分级虚拟插入的一种或多种技术和所得到的阵列。 例如，阵列是金属氧化物半导体（MOS）阵列，金属氧化物金属（MOM）阵列或电阻阵列。 在一些实施例中，基于与第一区域相关联的第一图案密度与与第二区域相关联的第二图案密度之间的密度梯度来识别第一区域和第二区域。 例如，第一图案密度和第二图案密度是门密度和/或多密度。 为此，在第一区域和第二区域之间插入虚拟区域，虚拟区域包括基于第一相邻图案密度和第二相邻图案密度的渐变图案密度。 以这种方式，提供分级虚拟插入，从而提高阵列的边缘单元性能。

公开(公告)号：US08546953B2

公开(公告)日：2013-10-01

申请号：US13324405

申请日：2011-12-13

申请人： Jaw-Juinn Horng ,  Chia-Lin Yu ,  Chung-Hui Chen ,  Der-Chyang Yeh ,  Yung-Chow Peng

发明人： Jaw-Juinn Horng ,  Chia-Lin Yu ,  Chung-Hui Chen ,  Der-Chyang Yeh ,  Yung-Chow Peng

IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L23/04 ,  H01L21/44

CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.

摘要翻译： 提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能传播通过半导体衬底的电噪声。 隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。 周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

公开(公告)号：US08242842B2

公开(公告)日：2012-08-14

申请号：US13364043

申请日：2012-02-01

申请人： Yu-Wei Lin ,  Yung-Chow Peng

发明人： Yu-Wei Lin ,  Yung-Chow Peng

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/45475 ,  H03F3/45632 ,  H03F3/45928 ,  H03F2203/45512 ,  H03F2203/45588

摘要： A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level.

公开(公告)号：US06888386B2

公开(公告)日：2005-05-03

申请号：US10127732

申请日：2002-04-23

申请人： Yung-Chow Peng

发明人： Yung-Chow Peng

IPC分类号： H03L7/089 ,  H03L7/18 ,  H03L7/06

CPC分类号： H03L7/0895 ,  H03L7/18

摘要： Charge-pumps consistent with this invention comprise a first transistor for sinking a current from an output node; a second transistor coupled between the first transistor and a ground node, wherein the second transistor interrupts the sinking current when the second transistor is turned off; and a current source to provide a turn-off current to a common node between the first transistor and the second transistor when the second transistor interrupts the sinking current. Charge-pump circuits consistent with this invention comprise a first transistor for sinking a current from an output node; a second transistor coupled between the first transistor and a ground node, wherein the second transistor interrupts the sinking current when the second transistor is turned off; and a clamping circuit to clamp a common node between the first transistor and the second transistor below a clamping voltage.

摘要翻译： 符合本发明的电荷泵包括用于从输出节点吸收电流的第一晶体管; 耦合在所述第一晶体管和接地节点之间的第二晶体管，其中当所述第二晶体管截止时，所述第二晶体管中断所述吸收电流; 以及电流源，当第二晶体管中断吸收电流时，向第一晶体管和第二晶体管之间的公共节点提供截止电流。 符合本发明的电荷泵电路包括用于从输出节点吸收电流的第一晶体管; 耦合在所述第一晶体管和接地节点之间的第二晶体管，其中当所述第二晶体管截止时，所述第二晶体管中断所述吸收电流; 以及钳位电路，用于将第一晶体管和第二晶体管之间的公共节点钳位在钳位电压之下。

公开(公告)号：US06297686B1

公开(公告)日：2001-10-02

申请号：US09321849

申请日：1999-05-28

申请人： Shi-Tron Lin ,  Yung-Chow Peng

发明人： Shi-Tron Lin ,  Yung-Chow Peng

IPC分类号： H03K301

CPC分类号： H03K19/01707 ,  H01L27/092 ,  H01L29/78609 ,  H03K19/0016

摘要： For low-voltage and high-speed operation of a MOSFET in an integrated circuit, a small voltage is applied to a source node, causing slight forward bias of the source junction and thereby reducing its threshold voltage. Due to the combined effects of the bias at the source node and a body effect, the reduction in threshold voltage is larger than the absolute value of the source voltage being applied. A performance improvement over simply applying a bias voltage to the body (well) results. Detection of an event can be used to apply the performance boost to a critical path in the integrated circuit only when needed. Upon detection of a logic event, which determines that a signal will propagate through the critical path shortly thereafter, the source-node bias for circuit elements in the critical path can be adjusted in time for a speed improvement. However, the source remains at another potential when no signal is passing through the critical-path, to save power when not boosting speed.

摘要翻译： 对于集成电路中的MOSFET的低电压和高速操作，向源节点施加小的电压，从而导致源极结的轻微的正向偏压，从而降低其阈值电压。 由于源节点偏置和物体效应的组合效应，阈值电压的降低大于施加的源极电压的绝对值。 通过简单地将偏置电压施加到身体（井），可以提高性能。 可以使用事件的检测来仅在需要时将性能提升应用于集成电路中的关键路径。 当检测到逻辑事件确定信号在此后不久将传播通过关键路径时，关键路径中的电路元件的源节点偏置可以及时调整以提高速度。 然而，当没有信号通过关键路径时，源保持在另一个潜力，以便在不提升速度时节省功率。

公开(公告)号：US06133863A

公开(公告)日：2000-10-17

申请号：US182752

申请日：1998-10-29

申请人： Yung-Chow Peng

发明人： Yung-Chow Peng

IPC分类号： H03M1/10 ,  H03M1/36 ,  H03M1/76

CPC分类号： H03M1/1033 ,  H03M1/365 ,  H03M1/765

摘要： A multiple reference voltages generation apparatus, which generates multiple reference voltages to an analog-to-digital converter (ADC), is provided. The apparatus includes a resistor-string and a control device. The resistor-string has a first terminal and a second terminal for connecting respectively with a first reference voltage and a second reference voltage. The resistor-string comprises a plurality of series-connected resistors which define a plurality of nodes for outputting the multiple reference voltages. A plurality of Bit-Decision-Node {n , where k=0, . . . (m-1), j is an odd positive integer and (2.sup.k .times.j) is smaller than 2.sup.m } determine accuracy of a corresponding output bit a.sub.k of the ADC. A corresponding reference voltage Vn is output at each Bit-Decision-Node. The control device adjusts the voltage V.sub.n on Bit-Decision-Node n to make V.sub.n -V.sub.n approximately equal to V.sub.n -V.sub.n , wherein BW(a.sub.k) is the weight value of the bit a.sub.k.

摘要翻译： 提供了向模数转换器（ADC）产生多个参考电压的多个参考电压产生装置。 该装置包括电阻串和控制装置。 电阻串具有分别连接第一参考电压和第二参考电压的第一端子和第二端子。 电阻串包括多个串联电阻器，其限定多个节点用于输出多个参考电压。 多个位决策 - 节点{n <2kxj>，其中k = 0。 的。 的。 （m-1），j是奇数正整数，（2kxj）小于2m}确定ADC的相应输出位ak的精度。 在每个比特决策 - 节点处输出相应的参考电压Vn <2kxj>。 控制装置调整位决策节点n <2kxj>上的电压Vn <2kxj>使Vn <2kxj + BW（ak）> -Vn <2kxj>近似等于Vn <2kxj> -Vn <2kxj-BW（ ak）>，其中BW（ak）是位ak的权重值。

公开(公告)号：US5933052A

公开(公告)日：1999-08-03

申请号：US954944

申请日：1997-10-22

申请人： Yung-Chow Peng ,  Gwo-Shu Chiou

发明人： Yung-Chow Peng ,  Gwo-Shu Chiou

IPC分类号： H03H19/00 ,  H04L25/06 ,  H03B1/00 ,  H03L5/00

CPC分类号： H03H19/004 ,  H04L25/062

摘要： An offset-free switched capacitor circuit selectively operated by a non-overlapping two-phase clock signal for processing a frequency shift keying (FSK) input signal is provided. The switched capacitor circuit includes a filter which inputs a voltage signal for generating an output signal which assumes a first voltage value Vt1 at the first phase of the clock signal and assumes a second voltage value Vt2 at the second phase of the clock signal. The output signal of the switched capacitor circuit is an input to a succeeding hysteresis limiter. The hysteresis limiter, which receives the difference of Vt2 and Vt1, is operative to generate a logic signal which is HIGH when an input signal thereof exceeds a HIGH.sub.-- ref signal and is LOW when the input signal thereof falls below a LOW.sub.-- ref signal, and is so operated that the offset voltage associated with the amplifier therein is counterbalanced via internal operation.

摘要翻译： 提供了通过用于处理频移键控（FSK）输入信号的不重叠的两相时钟信号有选择地操作的无偏移开关电容器电路。 开关电容电路包括滤波器，其输入用于产生在时钟信号的第一相位处呈现第一电压值Vt1的输出信号的电压信号，并且在时钟信号的第二相位处采用第二电压值Vt2。 开关电容电路的输出信号是对后续滞后限制器的输入。 接收Vt2和Vt1的差的滞后限制器用于产生当其输入信号超过HIGH-ref信号时为“HIGH”的逻辑信号，当输入信号低于LOW-ref信号时，该逻辑信号为“LOW” 并且被操作成使得与其中的放大器相关联的偏移电压通过内部操作平衡。