公开(公告)号：US20120032171A1

公开(公告)日：2012-02-09

申请号：US13193734

申请日：2011-07-29

申请人： Toshihiko SAITO ,  Yuki HATA ,  Kiyoshi KATO

发明人： Toshihiko SAITO ,  Yuki HATA ,  Kiyoshi KATO

IPC分类号： H01L27/088 ,  H01L29/786

CPC分类号： H01L27/124 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L28/40

摘要： An object is to miniaturize a semiconductor device. Another object is to reduce the area of a driver circuit of a semiconductor device including a memory cell. The semiconductor device includes an element formation layer provided with at least a first semiconductor element, a first wiring provided over the element formation layer, an interlayer film provided over the first wiring, and a second wiring overlapping with the first wiring with the interlayer film provided therebetween. The first wiring, the interlayer film, and the second wiring are included in a second semiconductor element. The first wiring and the second wiring are wirings to which the same potentials are supplied.

摘要翻译： 目的是使半导体器件小型化。 另一个目的是减小包括存储单元的半导体器件的驱动电路的面积。 半导体器件包括至少设置有第一半导体元件的元件形成层，设置在元件形成层上的第一布线，设置在第一布线上的中间膜，和与第一布线重叠的第二布线，设置有夹层膜 之间。 第一布线，层间膜和第二布线包括在第二半导体元件中。 第一布线和第二布线是提供相同电位的布线。

公开(公告)号：US20110298057A1

公开(公告)日：2011-12-08

申请号：US13117592

申请日：2011-05-27

申请人： Kiyoshi KATO

发明人： Kiyoshi KATO

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L27/11551 ,  G11C16/0466 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L28/60 ,  H01L29/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/78 ,  H01L29/7869

摘要： An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the semiconductor layer having the channel formation region and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction.

摘要翻译： 目的在于提供一种具有高度集成度的新型结构的半导体器件。 半导体器件包括具有沟道形成区域，与沟道形成区域电连接的源电极和漏电极的半导体层，与沟道形成区域重叠的栅极电极，以及沟道形成区域和沟道形成区域之间的栅极绝缘层 栅电极。 当从平面方向看时，具有沟道形成区域的半导体层的侧表面的一部分和源电极或漏电极的侧表面的一部分基本上对准。

公开(公告)号：US20110186949A1

公开(公告)日：2011-08-04

申请号：US13084996

申请日：2011-04-12

申请人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO ,  Takaaki KOEN ,  Yuto YAKUBO ,  Makoto YANAGISAWA ,  Hisashi OHTANI ,  Eiji SUGIYAMA ,  Nozomi HORIKOSHI

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO ,  Takaaki KOEN ,  Yuto YAKUBO ,  Makoto YANAGISAWA ,  Hisashi OHTANI ,  Eiji SUGIYAMA ,  Nozomi HORIKOSHI

IPC分类号： H01L29/66

CPC分类号： G06K19/07735 ,  G06K19/07722 ,  G06K19/07794 ,  H01L23/295 ,  H01L23/3157 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 Ω/cm2 is formed on at least one surface of each structure body.

摘要翻译： 一种能够进行无线通信的半导体装置，其在外力方面具有高的可靠性，特别是按压力，并且能够防止集成电路中的静电放电，而不会妨碍电波的接收。 半导体器件包括连接到集成电路的片上天线和将接收到的电波中包含的信号或功率发送到片上天线而不接触的增强天线。 在半导体器件中，集成电路和片上天线插入通过用树脂浸渍纤维体而形成的一对结构体之间。 其中一个结构体设置在片上天线和增强天线之间。 在每个结构体的至少一个表面上形成表面电阻值为大约106至1014Ω·cm 2 / cm 2的导电膜。

公开(公告)号：US20110128801A1

公开(公告)日：2011-06-02

申请号：US13024549

申请日：2011-02-10

申请人： Toshihiko SAITO ,  Kiyoshi KATO

发明人： Toshihiko SAITO ,  Kiyoshi KATO

IPC分类号： G11C7/00

CPC分类号： H01L27/1266 ,  B82Y10/00 ,  G06K19/07749 ,  G11C13/0014 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/79 ,  H01L27/12 ,  H01L27/1214 ,  H01L51/0591

摘要： In an organic memory which is included in a radio chip formed from a thin film, data are written to the organic memory by a signal inputted with a wired connection, and the data is read with a signal by radio transmission. A bit line and a word line which form the organic memory are each selected by a signal which specifies an address generated based on the signal inputted with a wired connection. A voltage is applied to a selected memory element. Thus writing is performed. Reading is performed by a clock signal or the like which are generated from a radio signal.

摘要翻译： 在由薄膜形成的无线电芯片中包括的有机存储器中，通过用有线连接输入的信号将数据写入有机存储器，并且通过无线电传输用信号读取数据。 构成有机存储器的位线和字线各自由指定基于由有线连接输入的信号生成的地址的信号来选择。 电压被施加到选定的存储元件。 因此执行写入。 通过从无线电信号生成的时钟信号等执行读取。

公开(公告)号：US20110101334A1

公开(公告)日：2011-05-05

申请号：US12912190

申请日：2010-10-26

申请人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC分类号： H01L27/108

CPC分类号： H01L27/088 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1225

摘要： It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.

摘要翻译： 本发明的目的是提供具有新颖结构的半导体。 在半导体器件中，多个存储器元件串联连接，并且多个存储元件中的每一个包括第一至第三晶体管，从而形成存储器电路。 包括氧化物半导体层的第一晶体管的源极或漏极与第二和第三晶体管之一的栅极电接触。 含有氧化物半导体层的第一晶体管的极低的截止电流允许长时间地在第二和第三晶体管之一的栅电极中存储电荷，由此可以获得基本上永久的记忆效应。 不含氧化物半导体层的第二和第三晶体管在使用存储电路时允许高速操作。

公开(公告)号：US20100253478A1

公开(公告)日：2010-10-07

申请号：US12754416

申请日：2010-04-05

申请人： Jun KOYAMA ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

发明人： Jun KOYAMA ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC分类号： H04Q5/22

CPC分类号： H04W52/028 ,  Y02D70/122 ,  Y02D70/166

摘要： An object is to provide a data processing device which achieves multiple functions or easy additional providing of a function while suppressing adverse influence on a communication distance or to improve resistance to electrostatic discharge in the data processing device. The data processing device includes an antenna which transmits and receives a first signal to/from a first terminal device through wireless communication, an integrated circuit which executes a process in accordance with the first signal, and a terminal portion which transmits and receives a second signal to/from a second terminal device and has an exposed conductive portion on its surface. A protection circuit is provided between at least one terminal of terminals of the terminal portion and a power supply terminal of a high potential and between the one terminal and a power supply terminal of a low potential.

摘要翻译： 本发明的目的是提供一种能够实现多种功能的数据处理装置，或容易地附加提供功能，同时抑制对通信距离的不利影响或提高数据处理装置中的静电放电的抵抗力。 数据处理装置包括通过无线通信向第一终端装置发送第一信号的接收天线，执行与第一信号对应的处理的集成电路以及发送接收第二信号的终端部 到/从第二终端设备，并且在其表面上具有暴露的导电部分。 在端子部分的端子的至少一个端子和高电位的电源端子之间以及在一个端子和低电位的电源端子之间提供保护电路。

公开(公告)号：US20100245306A1

公开(公告)日：2010-09-30

申请号：US12796067

申请日：2010-06-08

申请人： Jun KOYAMA ,  Kiyoshi KATO

发明人： Jun KOYAMA ,  Kiyoshi KATO

IPC分类号： G09G5/00

CPC分类号： H04W52/027 ,  G02F1/13454 ,  G09G3/30 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G5/006 ,  G09G2300/0408 ,  G09G2300/08 ,  G09G2310/027 ,  G09G2330/022 ,  H01L27/12 ,  H01L27/1214 ,  Y02D70/00

摘要： A semiconductor device capable of displaying a still image with low consumption power is provided. In the semiconductor device incorporated with a semiconductor display device capable of displaying the still image, a memory portion is mounted on a substrate on which a pixel portion is formed. As a mounting method, the memory portion is formed on the substrate on which the pixel portion is formed or a stick driver including the memory portion is used. When the still image is displayed using image data stored in such a memory portion, the still image can be displayed by inputting only simple control signals from the outside of the semiconductor device. Thus, there are provided the semiconductor display device capable of displaying the still image with low consumption power and the semiconductor device incorporated with the semiconductor display device.

摘要翻译： 提供能够以低功耗显示静止图像的半导体器件。 在结合有能够显示静止图像的半导体显示装置的半导体装置中，存储部安装在形成有像素部的基板上。 作为安装方法，存储部形成在其上形成有像素部的基板上，或者使用包括存储部的棒驱动器。 当使用存储在这种存储器部分中的图像数据显示静止图像时，可以仅通过从半导体器件的外部输入简单的控制信号来显示静止图像。 因此，提供了能够以低功率功率显示静止图像的半导体显示装置以及并入半导体显示装置的半导体装置。

公开(公告)号：US20100072286A1

公开(公告)日：2010-03-25

申请号：US12625618

申请日：2009-11-25

申请人： Kiyoshi KATO ,  Yasuyuki ARAI ,  Shunpei YAMAZAKI

发明人： Kiyoshi KATO ,  Yasuyuki ARAI ,  Shunpei YAMAZAKI

IPC分类号： G06K19/067 ,  H01L45/00

CPC分类号： G06K19/0723 ,  G11C13/0004 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144

摘要： The invention provides a semiconductor device including a memory of a simple structure to provide an inexpensive semiconductor device and a driving method thereof. The semiconductor device of the invention includes a phase change memory including a memory cell array having a plurality of memory cells, a control circuit that controls the phase change memory, and an antenna. The memory cell array includes a plurality of bit lines that extend in a first direction and word lines that extend in a second direction perpendicular to the first direction. Each of the plurality of memory cells includes a phase change layer provided between the bit lines and the word lines. In the semiconductor device having the aforementioned structure, one or both of a conductive layer that forms the bit lines and a conductive layer that forms the word lines transmits light.

摘要翻译： 本发明提供一种包括简单结构的存储器以提供便宜的半导体器件及其驱动方法的半导体器件。 本发明的半导体器件包括：相变存储器，包括具有多个存储单元的存储单元阵列，控制相变存储器的控制电路和天线。 存储单元阵列包括沿第一方向延伸的多个位线和在垂直于第一方向的第二方向上延伸的字线。 多个存储单元中的每一个包括设置在位线和字线之间的相变层。 在具有上述结构的半导体器件中，形成位线的导电层和形成字线的导电层中的一个或两个透射光。

公开(公告)号：US20090261173A1

公开(公告)日：2009-10-22

申请号：US12486838

申请日：2009-06-18

申请人： Shunpei YAMAZAKI ,  Kiyoshi KATO

发明人： Shunpei YAMAZAKI ,  Kiyoshi KATO

IPC分类号： G06K19/06

CPC分类号： H01L23/49855 ,  G06K19/07749 ,  G06K19/07758 ,  G06K19/07767 ,  G07D7/01 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides an ID chip with reduced cost, increased impact resistance and attractive design, as well as products and the like mounting the ID chip and a manufacturing method thereof. In view of the foregoing, an integrated circuit having a semiconductor film with a thickness of 0.2 μm or less is mounted on securities including bills, belongings, containers of food and drink, and the like (hereinafter referred to as products and the like). The ID chip of the invention can be reduced in cost and increased in impact resistance as compared with a chip formed over a silicon wafer while maintaining an attractive design.

摘要翻译： 本发明提供一种具有降低成本，增加耐冲击性和有吸引力的设计的ID芯片以及安装ID芯片的产品等及其制造方法。 鉴于上述，将厚度为0.2μm以下的半导体膜的集成电路安装在包括纸币，财物，食品和饮料容器等的证券（以下称为产品等）上。 与保持有吸引力的设计的硅晶片上形成的芯片相比，本发明的ID芯片可以降低成本并增加耐冲击性。

公开(公告)号：US20070127290A1

公开(公告)日：2007-06-07

申请号：US11672081

申请日：2007-02-07

申请人： Kiyoshi KATO

发明人： Kiyoshi KATO

IPC分类号： G11C16/04

CPC分类号： H01L27/1277 ,  G02F1/13454 ,  G11C16/0441 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1214

摘要： A nonvolatile memory capable of acting at each 1 bit and having a high integration density. A small-sized semiconductor device of multiple high functions having such nonvolatile memory. The nonvolatile memory is constructed to have a memory cell composed of two memory transistors so that it can realize a memory capacity of two times as large for a memory area as that of the full-function EEPROM of the prior art, in which the memory cell is composed of one memory transistor and one selection transistor, while retaining functions similar to those of the EEPROM. On the other hand, the small-sized semiconductor device of high functions or multiple functions is realized by forming the nonvolatile memory of the invention integrally with another semiconductor part over a substrate having an insulating surface.

摘要翻译： 一种非易失性存储器，能够在每1位作用并且具有高积分密度。 具有这种非易失性存储器的多个高功能的小型半导体器件。 非易失性存储器被构造成具有由两个存储晶体管组成的存储单元，使得其可以实现与现有技术的全功能EEPROM的存储区域相同的存储容量的两倍的存储容量，其中存储单元 由一个存储晶体管和一个选择晶体管组成，同时保留与EEPROM相似的功能。 另一方面，通过在具有绝缘表面的基板上与另一半导体部件一体形成本发明的非易失性存储器，实现了高功能或多功能的小型半导体器件。